Method and apparatus for generating expected value data for testing a circuit configured in a programmable logic device (PLD). A simulation model is generated from a circuit representation for the circuit. Nodes in the simulation model configured for readback capture are automatically identified. The circuit representation is simulated as defined by the simulation model. Expected value data is recorded during the simulation in response to the identified nodes. A method and apparatus for testing a circuit configured in a PLD is also described. Expected value data for components of a circuit representation for the circuit is automatically generated using a modeling system, where the components are configured for readback capture. A test stimulus is applied to the circuit and state data is captured. The captured state data is compared with the expected value data.

Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value. Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group. If a single error is detected, the error detection logic means for the function line groups indicate which group includes the erroneous function line. The mixed group error detection means similarly indicate, if appropriate, which of function lines of the mixed group is erroneous.

The design of a universally testable logic element from which combinational and sequential logic circuits can be formed is disclosed. The logic element is designed to operate as a NAND gate, NOR gate, or other functionally complete logic function in its normal mode. In a first test mode, the element functions like an OR gate. In a second test mode, the element functions like an AND gate. By building a circuit with such a logic element, the circuit can be tested for all classical stuck-at-zero and stuck-at-one faults with a minimal number of test patterns. Methods of testing both combinational and sequential circuits formed from such logic elements are also disclosed.

A multiple input logic gate that is amenable to full testability without the "buried logic" problem of conventional VLSI logic devices and a novel dynamic test method for increasing fault-free production and simplified analysis of sub-chip faults. In one disclosed illustrative embodiment of the logic gate of the invention, the device comprises a replicated, hierarchial arranged group of six two-variable input gates to form a three-variable input gate and two such three input gates and associated logic control structure are provided on a single VLSI integrated circuit chip. Each two-variable input gate is controlled by its own programmed logic array thereby providing a selection of any of the possible 256 Boolean functions for each of the three-variable input gates on a chip. A highly advantageous dynamic test method exploits the regular hierarchial architecture of the inventive logic gate to provide top-down evaluation of each two-variable input gate until the six-gate structure is fully tested. The test method is implemented by clocking the two-variable input gates through their respective sixteen Boolean function sequentially and displaying a video map of gate output signals which will conform to a specified pattern when the device is fault-free.

The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.