A digital oscillator generates a basic pulse having a period which is a predetermined large number of times of a clock pulse period. During the basic pulse period are allotted a predetermined small number of time slots defining submultiple frequency channels. There is provided a shift register having the channel number of stages, each stage being assigned to each channel. The contents of the respective stages are changed at respectively different periods which are multiples of the basic pulse period. The contents are taken out timewise-serially, one at a time, stage by stage, and superimposed on the basic pulse to constitute a time-division-multiplexed wave data signal. The delivered signal is demultiplexed to form individual waves having respectively different frequencies which are submultiple-related to the frequency of the basic pulse. This generator is very suitable for electronic musical instruments, as a single line transmits plural wave data.
A clock signal generator using fractional frequency division is provided comprising a division circuit that produces a clock signal starting from a timing rhythm signal. The frequencies of the two signals are in a division ratio which is the sum of a whole part and a fractional part. A pulse subtractor is provided for receiving the rhythm signal and transmitting it to the division circuit while deleting at least one pulse from this signal upon a command. An accumulator commands a pulse subtractor on each occasion when the product of the number of pulses of the clock signal counted, starting from a time of origin and of the fractional part, changes by unity.
An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.
A frequency generator for generating a large number of closely and evenly spaced frequencies over a large bandwidth including a first digitally controlled oscillator and a second digitally controlled oscillator, and a combiner for mixing the frequencies from said first and second digitally controlled oscillators, wherein the sampling rate of the digitally controlled oscillators differs by a small predetermined amount. Switching speed is extremely rapid.
A ring network of workstations interconnected on a single simplex ring is converted to duplex communications on the single ring by placing two transceivers in each workstation and adding a duplex conversion device between each workstation and its ring terminal box. One of the transceivers receives and retransmits signals in a clockwise direction around the ring; the other transceiver receives and retransmits signals in a counter-clockwise direction around the ring. The clockwise and counter-clockwise signals are superimposed on the ring but are isolated at the workstations by the duplex conversion device.
An imager (11) has a locate mode (13) which detects light (31A, 31B) having a preset light property from at least one locator (21) in the imager field of view (12); and has a react mode which is caused by the locate mode to select light from a code region (22, 32A, 32B, 33B) over light not from the code region (81) and which outputs a signal (41) representing code in the code region.
