A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.
A universal coupling unit for linking processing systems incorporating computers or processors with at least one peripheral unit. Each processing system has at least one processor and an exchange bus for exchanging information with the peripheral unit. The coupling units comprise bus controllers connected respectively to the exchange buses and to a local bus, itself connected to the peripheral unit by circuits for controlling exchanges of data and for processing control and state information. The bus controllers are able to manage the access protocols to the exchange buses, the information exchanges on the exchange buses and on the local bus, as well as any request made by a processor for access to the local bus. The control units comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus. Selection devices are connected to the bus controllers and controlled by the management microprocessor for selecting, as a function of the priorities, the controller able to ensure a data exchange on the local bus. An input and output buffer register is connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.
An interface circuit for an information processing device comprises a plurality of buffer circuits each formed of a plurality of C-MOS tri-state buffers. The buffers are provided for communicating between the devices and an interface line which includes a power supply line and a signal line. Each buffer is powered from its specific power source and if this specific power source is inoperative, from the remaining power sources other than its specific power source.
A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.
A distributed, fault-tolerant, self-repairable, reconfigurable signal processing system with redundant elements comprising signal processors, mass memories and input-output controllers interconnected by redundant busses forming a high reliability system. The input-output controller element has redundant busses for interconnecting multiple fault-tolerant distributed signal processing systems into a network configuration. One signal processor element in a system is initially designated as the executive and assigns processing tasks from a mass memory to the other elements or other systems. When a failure is detected, the executive verifies the failure, isolates the faulty element and reassigns the task to another spare element. If another element is not available, the executive reconfigures the system to permit degraded operation using the available elements. The executive element, itself, is fault monitored by one of the other elements which is capable of assuming the role of executive as required. The fault-tolerant and reconfiguration capabilities of the system result from a virtual addressing technique for each element, a distributed bus arbitration method and a two-level distributed operating system.
A multiple power supply sensor for protecting shared processor buses in a multiprocessor system. In the case that a power failure or power supply malfunction occurs in one of the processors of the system, at least one of the shared processor buses will be isolated from the malfunctioning processor. As a result, data on that bus is not corrupted by the manfunctioning processor. The isolation is accomplished by independent sensor circuits present in each processor for each bus.
