Information processing apparatus - Patent Review 4229768

Claims

What we claimed is:

1. Information processing apparatus, comprising: scanning means for obtaining binary image signals representing two light levels by scanning an original on which an image is recorded;

a selective thinning circuit for converting the signals representing either one light level in said binary image signals obtained by scanning operation by said scanning means and having a length in a principal scanning direction within determined ranges into signals of respectively determined lengths;

a run-length converting circuit for converting the signals of determined lengths obtained from said selective thinning circuit into signals of other lengths; and

a one-dimensional coding circuit for encoding the signals thus converted by said run-length converting circuit.

2. Information processing apparatus according to claim 1, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

3. Information processing apparatus, comprising:

scanning means for obtaining binary image signals representing two light levels by scanning an original on which an image is recorded;

a selective thinning circuit for converting the signals representing either one light level in said binary image signals obtained by scanning operation by said scanning means and having a length in the principal scanning direction within determined ranges into signals of determined lengths;

a run-length converting circuit for converting the signals of determined lengths obtained from said selective thinning circuit into signals of other lengths;

a one-dimensional coding circuit for encoding either of the signals of determined lengths obtained from said selective thinning circuit and the signals converted by said run-length converting circuit; and

a switch for supplying the signals of determined lengths obtained from said selective thinning circuit to either of said run-length converting circuit and said one-dimensional coding circuit.

4. Information processing apparatus according to claim 3, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

5. Information processing apparatus, comprising:

a scanning means for obtaining binary image signals representing two light levels by scanning an original on which an image is recorded;

pre-processing circuits for controlling inversion of the signals representing either one light level of said binary image signals obtained by scanning operation by said scanning unit to signals representing the other light level according to a state of said image;

a selective thinning circuit for converting the signals representing either one light level in said binary image signals after pre-processing and having a length in a principal scanning direction within determined ranges into signals of determined lengths; and

a one-dimensional coding circuit for encoding the signals obtained from said selective thinning circuit.

6. Information processing apparatus according to claim 5, wherein at least one of said pre-processing circuits comprises an isolated spot eliminating circuit for suppressing signal inversion which provides signals of either light level not exceeding a determined length and surrounded by signals of the other light level in said principal scanning direction and also in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

7. Information processing apparatus according to claim 5, wherein at least one of said pre-processing circuits comprises a main-scan smoothing circuit for suppressing signal inversion which provides signals of either light level not exceeding a determined length and surrounded by signals of the other light level in said principal scanning direction but connected at one side to the signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

8. Information processing apparatus according to claim 5, wherein at least one of said pre-processing circuits comprises a sub-scan smoothing circuit for controlling end positions of signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to the aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

9. Information processing apparatus according to claim 5, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

10. Information processing apparatus according to claim 6, wherein said pre-processing circuits further comprise a main-scan smoothing circuit for suppressing signal inversion which provides signals of either light level not exceeding a determined length and surrounded by signals of the other light level in said principal scanning direction but connected at one side to signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

11. Information processing apparatus according to claim 6, wherein said pre-processing circuits further comprise a sub-scan smoothing circuit for controlling end positions of signals of either color level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

12. Information processing apparatus according to claim 7, wherein said pre-processing circuits further comprise a sub-scan smoothing circuit for controlling end positions of signals of either color level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

13. Information processing apparatus, comprising:

scanning means for obtaining binary image signals representing two light levels by scanning an original on which an image is recorded;

pre-processing circuits for controlling inversion of signals representing either one light level of said binary image signals obtained by scanning operation by said scanning unit to signals representing the other light level according to a state of said image, said pre-processing circuit comprising:

an isolated spot eliminating circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by the signals of the other light level in said principal scanning direction and also in an auxiliary scanning direction substantially perpendicular to said principal scanning direction,

a main-scan smoothing circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by the signals of the other light level in said principal scanning direction but connected at one side to the signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction, and a sub-scan smoothing circuit for controlling end positions of the signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to the aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction;

a selective thinning circuit for converting the signals representing either one light level in said binary image signals after said pre-processing and having a length in the principal scanning direction within determined ranges

a run-length converting circuit for converting the signals of determined lengths obtained from said selective thinning circuit into signals of other lengths; and

a one-dimensional coding circuit for encoding the signals converted by said run-length converting circuit.

14. Information processing apparatus, comprising:

scanning means for scanning an original on which an image is recorded, to obtain binary image signals representing two light levels on first and second scan lines, thus obtaining first image signals and second image signals representing either one light level;

a selective thinning circuit for converting said first and second image signals obtained by scanning operation of said scanning unit and having a length in a principal scanning direction within determined ranges into signals of determined lengths;

a circuit for forming state signals representing the states of connections on said first and second scan lines of said first and second image signals obtained from said selective thinning circuit; and

an encoder for forming coded signals from said first image signals obtained from said selective thinning circuit and said state signals.

15. Information processing apparatus according to claim 14, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

16. Information processing apparatus according to claim 14, wherein said state signals represents four connection states.

17. Information processing apparatus according to claim 16, wherein said state signals comprise codes which are shorter for connection states of higher frequency of occurrence.

18. Information processing apparatus according to claim 16, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

19. Information processing apparatus, comprising:

a scanning means for scanning an original on which an image is recorded, to obtain binary image signals representing two light levels on first and second scan lines, thus obtaining first image signals and second image signals representing either one light level;

pre-processing circuits for controlling inversion of the signals representing either one light level among said binary image signals obtained by scanning operation by said scanning unit to signals representing the other light level according to a state of said image;

a selective thinning circuit for converting signals representing either one light level in said binary image signals after said pre-processing and having a length in a principal scanning direction within determined ranges to signals of determined lengths;

a circuit for forming state signals representing the connection states on said first and second scan lines of said first and second image signals obtained from said selective thinning circuit; and

an encoder for forming coded signals from said first image signals obtained from said selective thinning circuit and said state signals.

20. Information processing apparatus according to claim 19, wherein at least one of said pre-processing circuits comprises an isolated spot eliminating circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by the signals of the other light level in said principal scanning direction and also in an auxiliary scanning direction substantially perpendicular to sair principal scanning direction.

21. Information processing apparatus according to claim 19, wherein at least one of said pre-processing circuits comprises a main-scan smoothing circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by signals of the other light level in said principal scanning direction but connected at one side to signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

22. Information processing apparatus according to claim 19, wherein at least one of said pre-processing circuits comprises a sub-scan smoothing circuit for controlling end positions of the signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

23. Information processing apparatus according to claim 19, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

24. Information processing apparatus according to claim 19, wherein said state signals represents four connection states.

25. Information processing apparatus according to claim 20, wherein said pre-processing circuits further comprises a main-scan smoothing circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by signals of the other light level in said principal scanning direction but connected at one side to signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

26. Information processing apparatus according to claim 20, wherein said pre-processing circuits further comprises a sub-scan smoothing circuit for controlling the end positions of the signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

27. Information processing apparatus according to claim 21, wherein said pre-processing circuits further comprises a sub-scan smoothing circuit for controlling end positions of the signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction.

28. Information processing apparatus according to claim 24, wherein said state signals comprise codes which are shorter for connection states with higher frequency of occurrence.

29. Information processing apparatus according to claim 24, wherein said determined ranges comprise 3 to 5, 6 to 8 and 9 to 11 bits, said determined lengths being respectively 3, 6 and 9 bits.

30. Information processing apparatus, comprising:

scanning means for scanning an original on which an image is recorded, to obtain binary image signals representing two light levels on first and second scan lines, thus obtaining first image signals and second image signals representing either one light level;

pre-processign circuits for controlling inversion of the signals representing either one light level among said binary image signals obtained by scanning operation by said scanning unit to the signals representing the other light level according to a state of said image, said pre-processing circuits comprising:

an isolated spot eliminating circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by the signals of the other light level in a principal scanning direction and also in an auxiliary scanning direction substantially perpendicular to said principal scanning direction,

a main-scan smoothing circuit for suppressing the signal inversion which provides signals of either light level not exceeding a determined length and surrounded by the signals of the other light level in said principal scanning direction but connected at one side to the signals of said either one light level in an auxiliary scanning direction substantially perpendicular to said principal scanning direction, and

a sub-scan smoothing circuit for controlling end positions of the signals of either light level in said principal scanning direction and displacing said end position in said principal scanning direction so as to coincide with the end position of other signals for the same light level located adjacent to aforementioned signals at least on one side thereof in an auxiliary scanning direction substantially perpendicular to said principal scanning direction;

a selective thinning circuit for converting the signals representing either one light level in said binary image signals after said pre-processing and having a length in the principal scanning direction within determined ranges to the signals of determined lengths;

a circuit for forming state signals representing the connection states on said first and second scan lines of said first and second image signals obtained from said selective thinning circuit; and

an encoder for forming coded signals from said first image signals obtained from said selective thinning circuit and said state signals.

31. Information processing apparatus, comprising:

scanning means for obtaining binary image signals representing two light levels by scanning an original on which an image is recorded;

a plurality of memory means for storing each of said binary image signals obtained by scanning operation by said scanning unit;

counting means for counting the number of signal runs each of which is stored in said plurality memory means, is time-sequentially continuous and represents either one light level;

connecting means controlled by an output of said counting means for connecting adjacent two of said memory means;

a run-length converting circuit for converting signals of determined lengths supplied through said connecting means and said plurality of memory means into signals of other lengths; and

a one-dimensional coding circuit for encoding the signals converted by said run-length converting circuit.

32. Information processing apparatus according to claim 31, further comprising a switch which supplied signals of determined lengths supplied through said connecting means and said plurality of memory means to either of said run-length converting circuit and said one-dimensional coding circuit.

33. Information processing apparatus according to claim 31, further comprising pre-processing circuits for controlling inversion of the signals representing either one light level among said binary image signals obtained by scanning operation by said scanning unit to the signals representing the other light level according to a state of said image, and for supplying the output signals of said pre-processing circuits to said memory means.

34. Information processing apparatus, comprising:

scanning means for scanning an original on which an image is recorded, to obtain binary image signals representing two light levels on first and second scan lines, thus obtaining first image signals and second image signals representing either one light level;

plurality of memory means for storing each of said binary image signals obtained by scanning operation by said scanning unit;

counting means for counting the number of signal runs each of which is stored in said plural memory means, is time-sequentially continuous and represents either one light level;

connecting means controlled by the output of said counting means connecting adjacent two of said memory means;

a circuit for forming state signals representing connection states on said first and second scan lines of said first and second image signals supplied through said connecting means and said plurality of memory means; and

an encoder for forming coded signals from said first image signals supplied through said connecting means and said plurality of memory means and said state signals.

35. Information processing apparatus according to claim 34, further comprising pre-processing circuits for controlling inversion of the signals representing either one light level among said binary image signals obtained by scanning operation by said scanning unit to signals representing the other light level according to a state of said image, and for supplying the output signals of said pre-processing circuits to said memory means.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information processing apparatus in which a signal compression ratio is increased without deterioration in image quality by means of a selective thinning process in transmission of binary image signals obtained by scanning of an original document.

2. Description of the Prior Art

In a conventional facsimile apparatus as shown in FIG. 1, the black-and white information recorded on an original document, not shown, is converted, by scanning with a scanner A1, into time-serial binary image or picture signals consisting of a "0" signal representing a white or highlight dot and a "1" signal representing a black or shadow dot. A bandwidth compressor B1 compresses the binary image signals by alloting a code to each of the signals according to the run-length thereof. The thus coded signals are modulated by a modulator C1 into telephone line transmittable signals, i.e. AC signals within a determined frequency band width, and transmitted through a telephone line LT1.

In such facsimile apparatus it is not possible to expect a higher signal compression since the run-lengths of black or white picture elements are faithfully coded. There can be considered various processes, therefore, in order to improve signal compression ratio.

For example in the case of an existence of isolated spots, such as dusts or stains, on an original, the improvement in the compression ratio cannot be expected in the facsimile apparatus shown in FIG. 1 since such noise components are faithfully transmitted in such apparatus. For removing such noise components, therefore, there can be considered a process of eliminating such isolated spots.

Also in conversion of a boundary between black and white areas into binary image signals, there may often result so-called quantizing errors due to unstable identification of black or white levels. It is in fact not only meaningless but also detrimental to the improvement in the signal compression ratio to faithfully encode the binary image signals containing such quantizing errors.

In order to avoid such quantizing errors, there can be considered a smoothing process on such boundaries, which can be applied both in the principal or horizontal scanning direction (as represented by the arrow SC1 in FIG. 3A) and in the auxiliary or vertical scanning direction (as represented by the arrow SC2 in FIG. 3A).

Further, in image or picture information composed of letters, numerals, symbols etc. (hereinafter collectively called "characters"), it is difficult to improve the signal compression ratio is the line thickness is exactly coded despite of the fact that the line thickness of a character has no relation with the meaning thereof. However a socalled thinning process, which eliminates the information representing the line thickness and thus reduces the line thickness of black picture elements to a thickness of approximately one picture element, will inevitably lead to a deterioration in image quality. A more complicated structure of the apparatus though such a process will allow to improve the signal compression ratio. For example FIGS. 3A and 4A respectively show enlarged views of binary coded characters "mbre" and "fo". After the aforementioned elimination of isolated dots and smoothing followed by the aforementioned thinning process, the image quality will be significantly deteriorated as shown in FIGS. 3B and 4B. It will be understood that the character "r" in FIG. 3B lacks the portion P1, and the character "f" in FIG. 4B lacks the portion P2 or horizontal bar. Besides the thinned image as shown in FIG. 3B or FIG. 4B has to be thickened again in the facsimile receiver to obtain a restored image as shown in FIG. 3C or 4C, so that the apparatus inevitably bocomes complicated. For these reasons a signal processing without the drawbacks of the conventional thinning process has been longed for.

SUMMARY OF THE INVENTION

A first object of the present invention is to reduce a deterioration in image quality which would frequently result from a signal compression process.

A second object of the present invention is to improve a signal compression ratio while thus reducing a deterioration in image quality.

A third object of the present invention is to simplify the structure of the signal processing apparatus thereby improving the reliability and reducing the cost thereof.

A fourth object of the present invention is to provide signal processing apparatus applicable to a coding method of a high signal compression as well as of wide popularity.

A fifth object of the present invention is to provide a thinning process effective also for a graphic information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a conventional information processing apparatus;

FIG. 2A is a schematic block diagram of an information processing apparatus of the present invention;

FIG. 2B is a schematic block diagram of an image process or;

FIG. 3A is an enlarged view of a binary coded original pattern;

FIG. 3B is an enlarged view of the binary coded pattern after a thinning process;

FIG. 3C is an enlarged view of the pattern of FIG. 3B after a thickening process;

FIG. 4A is an enlarged view of another binary coded original pattern;

FIG. 4B is an enlarged view of the pattern after a thinning process;

FIG. 4C is an enlarged view of the pattern of FIG. 4B after a thickening process;

FIG. 5A is a schematic block diagram showing circuitry for eliminating isolated spots;

FIG. 5B is an enlarged view of a black isolated spot;

FIG. 5C is an enlarged view of a white isolated spot;

FIG. 6A is an enlarged view of a binary coded original pattern;

FIG. 6B is an enlarged view of the binary coded pattern after an image processing;

FIGS. 7A(a)-7A(c), when combined as shown in FIG. 7, are a circuit diagram showing an arrangement for smoothing process in the principal scanning direction;

FIG. 7B is a view of a convexly contoured black image;

FIG. 7C is a view of a concavely contoured black image;

FIG. 7D is an enlarged view of a downward concave balck image;

FIG. 7E is an enlarged view of an upward concave black image;

FIG. 8A is a schematic block diagram showing an arrangement for smoothing process in the auxiliary scanning direction;

FIG. 8B is a view showing the left-hand end and the right-hand end of a black image;

FIG. 8C is an enlarged view showing a black image convex to the right;

FIG. 8D is an enlarged view of a black image concave to the right;

FIG. 8E is an enlarged view of a black image convex to the left;

FIG. 8F is an enlarged view of a black image concave to the left;

FIG. 9A is a chart plotting the number of occurrences of black run-lengths in an original;

FIG. 9B is a chart plotting the number of occurrences of black run-lengths after a ternary selective thinning process;

FIG. 9C is a chart plotting the number of occurrences of black run-lengths after a unitary selective thinning process;

FIG. 10A is an enlarged view of a binary coded original pattern;

FIG. 10B is an enlarged view of the binary coded pattern after a pre-processing followed by a unitary selective thinning process;

FIG. 10C is an enlarged view of the binary coded pattern after pre-processing followed by a ternary selective thinning process;

FIG. 11A is an enlarged view of another binary coded original pattern;

FIG. 11B is an enlarged view of the binary coded pattern after a pre-processing followed by a unitary selective thinning process;

FIG. 11C is an enlarged view of the binary coded pattern after a pre-processing followed by a ternary selective thinning process;

FIG. 12 is a circuit block diagram showing an arrangement for a ternary selective thinning process;

FIG. 13A is a table showing the terminate codes;

FIG. 13B is a table showing the make-up codes;

FIG. 14 is a plot showing the deviation in code length and the percentage occurrence of black runs as a function of black run-length;

FIG. 15A is a schematic block diagram of a bandwidth compressor for the MH coding;

FIG. 15B is a schematic block diagram of a bandwidth compressor for the MMH coding;

FIG. 15C is a schematic block diagram of a bandwidth compressor for both MH and MMH coding;

FIGS. 16A-16C are views showing the various states of combination of black runs;

FIG. 17A is a view showing binary image signals of two scan lines;

FIG. 17B is a view showing the binary image signals after the MMH coding;

FIG. 17C is a view showing the positions for classifying the binary image signals into various states; and

FIG. 18 is a schematic block diagram showing circuitry for second coding.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A and 2B show the schematic block diagrams of the information processing apparatus in accordance with the present invention. In FIG. 2A, a scanner A2 scans the black-and-white information recorded on an unrepresented original to convert the information into time-serial binary image or picture signals composed of "0" signals corresponding to white or highlight portions and "1" signals corresponding to black or shadow portions. The binary image signals are supplied to a picture processor E in which the signals are subjected to the processes of elimination of isolated spots and smoothing, and further to a ternary selective thinning process for classifying the run-length of signals into three ranges as will be explained later. These processes are conducted to supplement or delete information to or from the binary image signals in such a manner as to achieve a significant signal compression or a reduction in transmission time practically without deterioration of image quality. A bandwidth compressor B2 performs coding and compression by allotting, to thus processed signals, certain codes corresponding to the length of said signals. The thus coded signals are modulated in a modulator C2 and transmitted over a telephone line LT2. The signals thus transmitted are received by a receiver, not shown, to reassemble the original image.

The picture processor E shown in FIG. 2A comprises, as shown in FIG. 2B, a spot eliminator E1 for eliminating isolated information constituting a noise component in the image or picture signals, a main or principal scanning smoothing circuit E2 for suppressing the inversion of signals "0" and "1" appearing in the principal scanning direction (as represented by the arrow SC1 in FIG. 3A), a sub-scanning or auxiliary scanning smoothing circuit E3 for suppressing the inversion of signals "0" and "1" appearing in the auxiliary scanning direction (as represented by the arrow SC2 in FIG. 3A), and a selective thinning circuit E4 (a ternary selective thinning circuit in the present embodiment) for converting image signals of a run-length within a determined range into image signals of a determined length. The above-mentioned circuits E1-E4 are mutually independent and may be connected in an interchanged order, for example in the order of E2, E3, E1 and E4 from left to right in FIG. 2B. It is to be noted, however, that the compression ratio of the obtained signals becomes different in such an interchanged order.

The functions of circuits E1-E4 shown in FIG. 2B will be explained more detailedly in the following.

FIG. 5A shows the internal structure of spot eliminating circuit E1 which improves the signal compression ratio by eliminating noises consisting of isolated signal "0" or "1" from the binary image signals.

FIGS. 5A and 5B show the patterns of nine neighboring picture elements 14Q-22Q or 14'Q-22'Q which respectively correspond to the signals from the outputs Q of the flip-flops 14F-22F shown in FIG. 5A. It is assumed that the signals "0" and "1" respectively represent white and black picture elements. In FIG. 5B the isolated black picture element which is less than a predetermined length and corresponds to the signal "1" in the picture element 18Q can be eliminated by inverting signal "1" (black) to "0" (white). Similarly in FIG. 5C the isolated white picture element which is less than a predetermined length and corresponds to the signal "0" in the picture element 18'Q can be eliminated by inverting signal "0" (white) to "1" (black). The crosses "X" in FIG. 5C indicate that signals in these picture elements may be either "0" or "1". The circuit shown in FIG. 5A functions to eliminate the isolated spot in the information from the output Q of the flip-flop 18F as explained in the foregoing and to supply thus modified signals to the input D of the flip-flop 19F. In the circuit of FIG. 5A, the aforementioned binary image signals are entered bit by bit from an input line Li.sub.1 in synchronism with the original scanning and are in succession transferred in the order of flip-flops 14F-16F, a buffer memory 23, flip-flops 17F-19F, a buffer memory 24 and flip-flops 20F-22F in response to the clock pulses supplied from a clock line Lc1. In this manner the binary image signals on the first scan line are stored in the flip-flops 22F, 21F and 20F and in the buffer memory 24, while the binary image signals on the second scan line are stored in the flip-flops 19F, 18F and 17F and in the buffer memory 23, and the first three binary image signals on the third scan line are stored in the flip-flops 16F, 15F and 14F. Thus buffer memories 23, 24, usually composed of shift registers, respectively have a memory capacity equal to the number of bits in a scan line minus three bits, thereby allowing to identify the inter-line correlation of the information consisting of three scan lines. Through the above-mentioned arrangement of the flip-flops 14F-22F and the buffer memories 23 and 24, flip-flops 14F-22F respectively correspond to the positions of the nine picture elements 14Q-22Q or 14'Q-22'Q shown in FIG. 5B or 5C. Now, taking the pattern shown in FIG. 5B or 5C as the original, the first scan line, which will hereinafter be called the preceding line, extends in the direction of arrow SL1, while the second scan line, which will hereinafter be called the subject line, extends in the direction of arrow SL2, and the third scan line, which will hereinafter be called the succeeding line, extends in the direction of arrow SL3.

In the circuit shown in FIG. 5A, the spot eliminating process is conducted at the flip-flop 18F, since the spot to be eliminated appears always in the central picture element in FIGS. 5B and 5C. In FIG. 5A, 25 and 28 are AND circuits, 26 in a NAND circuit, and 27 is an OR circuit. As the output ports Q of flip-flops 14F-17F and 19F-22F are connected to the NAND circuit 26, it gives an output "0" when the output ports Q of said flip-flops provide outputs "0", or namely when the output ports Q of the flip-flops provide outputs "1". In each flip-flop the input port D and the output port Q are always on a same signal level, while the output ports Q and Q are always on inverted signal levels. The AND circuit 28, of which an input port is connected to the output port of said NAND circuit 26, therefore gives an output "0" regardless of the output signal from the flip-flop 18F which is received at the other input port of said AND circuit 26 through the OR circuit 27. Upon an entry of the succeeding image signal through the input line Li.sub.1 to the input port D of the flip-flop 14F and of a clock pulse from the clock line Lc1, the input port D of the flip-flop 18F receives the signal from the output port Q of the flip-flop 17F while the input port D of the flip-flop 19F receives the signal "0" regardless of the output from the flip-flop 18F. In this manner the signal transmission is achieved with the elimination of the isolated spot at the flip-flop 18F, or namely with the elimination of the isolated black spot "1" in FIG. 5B. Also as the output ports Q of the flip-flops 15F, 17F, 19F and 21F are connected to the AND circuit 25, it provides an output "1" when output ports Q provide output "1". Thus the OR circuit 27, of which an input port is connected to the output port of AND circuit 25, therefore gives an output "1" regardless of the output signal from the flip-flop 18F which is received at the other input port of OR circuit 27. Also as the output port Q of the flip-flops 15F, 17F, 19F and 21F are connected to the NAND circuit 26, it provides an output "1" when the output ports Q of the flip-flops provide output "0", namely when the output ports Q of the flip-flops provide output "1". The AND circuit 28, of which an input port is connected to the output port of NAND circuit 26 while the other input port is connected to the output port of OR circuit 27, always provides an output "1" regardless of the output from flip-flop 18F. Upon entry of the succeeding signal through the input line Li1 to the input port D of the flip-flop 14F and of a clock pulse through the clock line Lc1, the input port D of the flip-flop 18F receives the signal from the output port Q of the flip-flop 17F, while the input port D of the flip-flop 19F receives a signal "1" regardless of the output from the flip-flop 18F. In this manner the signal transmission is achieved with the elimination of the isolated spot at the flip-flop 18F, or namely with the elimination of the isolated white spot "0" in FIG. 5C.

FIG. 6A shows in an enlarged view a binary coded original pattern of characters "mb". The above-explained spot elimination allows to remove noises from the image as shown in FIG. 6B, thus eliminating a black picture element in the area P3 and a white picture element in the area P4 as shown therein.

FIG. 7A shows the internal structure of the aforementioned smoothing circuit E2 shown in FIG. 2B, which improves the signal compression ratio by detecting and suppressing the change of signals "0" and "1" in the principal scanning direction as represented by the arrow SL1.

FIGS. 7B-7E show black image patterns having convex or concave portions directed upward or downward. Such convex or concave portions are smoothed by investigating the connection of black picture elements in the subject scan line (arrow SL2) with the black picture elements in the preceding scan line (arrow SL1) and with those in the succeeding line (arrow SL3), and by changing the black pictur