Disclosed is a cell to word buffer for use in a digital TV display radar system in which radar pulse returns are digitized by an analog to digital converter to form pixel data, polar coordinates of the pulse returns are converted to their equivalent X, Y cartesian coordinates by a coordinate converter and the pixel data are stored in an X, Y refresh memory array in accordance with their X, Y coordinates for use in refreshing a TV display. The cell to word buffer allows large offsets in high resolution radar scan converters. The cell to word buffer memory means is located intermediate the coordinate converter and refresh memory for temporarily storing, for each Y location, a plurality of groups of adjacent pixel data and their associated X addresses and for transferring each group of pixel data to its appropriate location in the refresh memory when each group in the buffer memory is filled with pixel data. Further buffer registers of the first in, first out type may be provided intermediate the buffer memory and the refresh memory for smoothing the rate of data transfers therebetween. Also, peak detection means may be provided to avoid loss of pixel data for radar samples near the origin.

A single-cluster lamp drive device makes use of a controller to receive video data from a control system and then divides the video data into three sub video data. Next, these three sub video data are simultaneously and repetitively outputted to a digital-to-analog converter in every fixed time interval. Subsequently, the digital-to-analog converter converts these three sub video data to three analog voltages outputted to a voltage-to-current converter. Finally, the voltage-to-current converter converts these three analog voltages to three analog currents for driving light emitting devices to emit light, hence accomplishing voltage-in-current-out driving. The drive device drives a single-cluster lamp composed of one LED or several LEDs to adjust their brightness through current change, thereby coordinating with the control system to produce various color and pattern variations.

A display memory control system is disclosed which is associated with a display system for displaying and outputting character data, graphic data and the like. In the event of displaying images on a display, a system (host computer) writes one screen of display data in one of two VRAMs. The display data are transferred to the display and to the other VRAM to be stored therein. Upon completion of the storage in the other VRAM, the display data stored therein are read out to appear on the display. To update the display data, the system makes a write access to the one VRAM within a period of time other than one for which the transfer of video data is effected from the one VRAM to the other VRAM. This increases the period of time within which the one VRAM is accessible by the system and, thereby, enhances high speed data processing and display of high resolution images on the display with a desirable quality.

A raster-scan display device (which may be part of a combined raster-scan/calligraphic display) has a store (8) which is loaded (calculators 2, 4, 5, and 7) with image data. Processing of the data to assemble and output sets of values corresponding to successive lines of the display is performed by line processors (10, 11, 12, etc.): during output of one line or part-line by a processor, image data for a subsequent line or part of a line is being processed by another processor, so that a processing time in excess of one line duration is available. One application of such devices is in flight simulators.

A video computing system is disclosed having an automatically refreshed memory. The computing system includes a dynamic memory connected to a cathode ray tube. A cathode ray tube controller is also connected to the memory and is capable of sequentially generating addresses, corresponding to locations in the memory. A central processor is connected to the dynamic memory and operates on an alternating, two phase fetch and execute cycle. During the fetch phase, the central processor has access to the dynamic memory, while during each execute phase, when computing operations are carried out, access to the dynamic memory is prevented. In contrast, during the execute phase, the cathode ray tube controller is permitted direct access to the memory enabling the video information stored therein to be supplied to the cathode ray tube. The sequential and continuous reading of the memory during each execute phase functions to continually refresh the dynamic memory.