A photosensor device having a semiconductor layer disposed on a substrate. The semiconductor layer includes a lateral photosensor having a semiconductor junction arranged in a serpentine configuration and a lateral read-out switch. The lateral read-out switch and the lateral photosensor are formed on the semiconductor layer. The lateral photosensor has an area of a first conductivity type semiconductor and an area of a second conductivity type semiconductor. The lateral read-out switch includes an area of the first conductivity type and an area of the second conductivity type. The lateral photosensor and the lateral read-out switch are laterally adjacent, and substantially coplanar on the substrate.

The invention proposes a simple method to lower the threshold voltage of UV erased EPROM and OTP memories. During the erasure, a voltage is applied to the control gate (10) or wordline (2) which is on-chip generated as a photovoltage by means of photodiode (12) irradiated by radiation (15) during erasure. Because the wordlines are coupled to further zones forming photosensitive pn-junctions in the semiconductor body, measures are taken to prevent that, due to charge transport across said junctions, the generated photovoltage is decreased too strongly.

A charge-coupled device comprises transfer gate electrodes separated from a substrate by a multi-layer insulating film, and gate electrodes of MIS transistors separated from the substrate by a single layer insulating film. The multilayer insulating film comprising at least a lower silicon oxide layer of 10 nm to 200 nm thickness and an upper silicon nitride layer of 10 nm to 100 nm thickness. Since each of the gate insulating films of the MIS transistors is the same layer as the lower silicon oxide layer, there occurs no degradation in the transistor characteristics due to the surface states or the trapping states present within the silicon nitride layer.

A semiconductor photodetector device comprises an insulating gate field effect transistor having a gate in which a PN junction (J) is formed on an insulating layer. The gate is formed of a gate electrode (14) of P.sup.+ -type single crystalline silicon and a gate extension portion (17) of N.sup.+ -type single crystalline silicon. Electric charges generated by a light falling on an area including the PN junction are accummulated in the gate electrode (14). A signal of the accumulated electric charge is amplified by the transistor to obtain an output signal (V.sub.out) for detection.

A charge-coupled device has a multi-layer structure insulating layer is formed beneath a transfer electrode, floating electrodes and an electrode adjacent the floating electrodes so that pin hole phenomenon in a charge transfer section of the charge coupled device can be successfully prevented. On the other hand, a sole-layer structure insulating layer is formed beneath a gate electrode of a peripheral component so that a threshold voltage of the gate electrode of the peripheral component can be successfully controlled at a desired value.