An operational amplifier having a differential signal input and an output has an input stage comprising a differential amplifier having a differential signal input and a differential signal output. The differential amplifier includes a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential signal input, and second and third pairs of transistors of opposite conductivity type having control elements connected to receive another side of the differential signal input. The differential output of the differential amplifier is developed by outputs of the second and third pairs of transistors. A high-swing output section is connected to receive the differential signal output directly from the input stage. The differential amplifier has first and second current sources connected respectively between transistors of the first, second and third transistor pairs of a first conductivity type and a voltage supply, and between transistors of the first, second and third transistor pairs of a second conductivity type and a reference potential. A summing circuit is also provided in the input stage for summing the currents in the first, second, and third transistor pairs to produce the differential output of the input stage. The operational amplifier can be constructed of either bipolar or MOS transistors. One embodiment of the circuit provides an improved power supply rejection ratio through the use of current mirrors in a differential summing circuit to maintain output nodes of the input circuit at voltages within 2V.sub.BE of the supply voltage and reference potential, or ground.

A differential pair having a current source for providing amplification and slewing currents and a large signal circuit responsive to the differential pair input signals for shunting slewing current from the current source away from the differential pair for low input differential and linearly varying the amount of slewing current to be provided from the current source to the differential pair for higher input differentials.

A Class-A complementary metal oxide semi-conductor (CMOS) operational amplifier is provided having an improved slew rate. The preferred embodiment of the invention utilizes a CMOS amplifier circuit and an external capacitor, which together exhibit relatively poor sourcing of current and hence a relatively low positive slew rate in response to an input signal being more positive than an output signal of the CMOS amplifier by a relatively large amount. The disparity between the input and output signals defines an error signal. The present invention also includes a supplemental output stage communicating with the amplifier circuitry and the external capacitor. The supplemental output stage is activated in order to supply additional sourcing current, thereby increasing the positive slew rate, when a relatively large error signal is present and is de-activated otherwise. The present invention can also provide an improved negative slew rate in a CMOS amplifier circuit and an external capacitor, which together exhibit poor sinking of current in response to the input signal being more negative than the output signal by a relatively large amount.

An input stage of an operational amplifier uses current sources to allow first and second differential input transistor pairs to operate near the power supply rails. The output stage of the operational amplifier also operates within a saturation potential of the power supply rails. The first differential input transistor pair operates when the input signal is less than a predetermined threshold, while the second differential input transistor pair operates when the input signal is greater than the predetermined threshold. A detection circuit at the input terminals prevents phase inversion of the output signal should the inputs be driven beyond the power supply rails. A current cancellation circuit removes current variation induced by voltage changes at the output of the input stage and provides high gain and low input offset voltage.

A driving circuit for a two-phase brushless motor which includes a magnetized rotor, first and second magnetically sensitive elements disposed adjacent the rotor, and a pair of driving coils. The magnetically sensitive elements are coupled in series with one another and a bias voltage is applied thereto. First and second differential pairs of transistors receive inputs from the first and second magnetically sensitive elements, respectively, and the first and second differential pairs are coupled in series with one another and a constant current is applied thereto. Current mirror circuits produce currents in proportion to the currents flowing in the first and second differential pairs and output drivers energize the coils of the motor in response to outputs of the current mirror circuits.