The disclosed MOS transistor includes a channel region formed of a lightly doped semiconductor layer disposed in a surface portion of a heavily doped semiconductor layer subsequently disposed on a lightly doped semiconductor substrate. The channel region may be of the identical or opposite conductivity type to the heavily doped semiconductor layer that has the same type conductivity as the substrate. Also the channel region may be of an intrinsic semiconductive material. A source and a drain region may be disposed in the lightly or highly doped layer. Alternatively the source and drain regions may reach the substrate.
An insulated gate field effect transistor, in which at least the drain region is surrounded by an impurity region of the same conductivity type as and a higher impurity concentration than the substrate, is disclosed. A portion of the impurity region under the drain region contains both of P-type and N-type impurities to form an abrupt profile therby depleting the portion with a depletion layer by the built-in potential.
A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.
A VLSI enhancement mode metal oxide semiconductor field effect transistor operative to be Normally-On except during those periods when a negative threshold voltage is applied to the gate electrode. A submicron MOSFET channel having relatively high resistivity substrate allows for source and drain PN junction with overlapping depletion regions to create an electric field that promotes a surface inversion layer in the channel for conduction between the source and drain in a Normally-On mode except upon application of a negative gate threshold that acts to invert the channel surface to a non-conducting mode.
A semiconductor device includes a p-type semiconductor layer, a punch-through stopper layer having a positive impurity concentration and formed on an upper side of the p-type semiconductor layer, a buried layer formed on an upper surface of the punch-through stopper layer in a channel region, N-type source and drain regions of an LDD construction sandwiching the buried layer therebetween, a gate oxide film formed on the buried layer, and a gate electrode opposed to the buried layer, with a gate oxide film therebetween, wherein the punch-through stopper layer is shallower than the drain region.
This invention relates to a process for fabricating a metal-oxide-semiconductor device and to the semiconductor device which has enhanced charge mobility due to the inclusion of a thin layer of intrinsic semiconductor which provides a "fast track" charge channel directly at the accumulated inversion layer. The particular semiconductor device described is the enhanced mobility metal-oxide-semiconductor field effect transistor EMMOSFET having the intrinsic layer from about 100 .ANG. to about 1000 .ANG. thick. The intrinsic layer provides a low resistivity channel between the source and drain of the EMMOSFET resulting in an increase in device speed and a decrease in device heat generation.
