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DESCRIPTION
1. Technical Field
In the past, large and complex logic circuits were built up of relatively
small and simple units. Manufacturing and diagnostic testing of such
smaller units as well as the larger ones were routinely done without much
complexity. This was possible because of the prevailing accessibility to
the body of the circuitry both for the application of test stimuli and for
the probing and examination of circuit responses. Occasionally, some
normally interior points were specially brought out to convenient
locations explicitly for testing purposes. such design diversions rarely
amounted to any substantial problem.
With the advent of large-scale integration (LSI), however, direct
accessibility to the body of a group of circuits in any physical unit such
as a chip or module becomes greatly limited. This is because of the vastly
increased number of circuits included within an LSI unit and also because
of the microscopic dimensions these circuits now assume. Testing such
circuitry is a major concern in the electronics industry. The problem of
testing an LSI unit is further aggravated by the presence of the now
inaccessible storage elements or latches which are regularly embedded
among the combinatorial logic networks. Without an assured way of setting
and examining the logic states of such embedded latches, there can be no
testing of the associated logic networks. Yet, a reliable and thorough
testing of all LSI units is indispensible in manufacturing as well as in
maintenance. Several recent inventions listed in the "Background Art"
section provide system design methods and disciplines that answer the
above need. They all come under the generic title LSSD (Level Sensitive
Scan Design). The common main thrust of these inventions is to prescribe a
built-in capability for every LSI unit, such as chip module etc., whereby
the entire logic state of the unit, when under test, can be explicitly set
and/or examined through exercising certain input/output (I/O) procedures
at a limited number of I/O terminals. This requirement is implementible by
imparting a shift-register capability to every one of the logic system
latches in the unit and thereupon organizing these shift register latches
(SRL) into one or more shift register data channels with their terminal
stages accessible to the outside world. Details of operations using the
SRL facility for various aspects of the testing purposes are given in most
of the aforementioned patents. Particular reference may be made to FIG. 8
of U.S. Pat. No. 3,761,695 and FIGS. 7, 8 and 9 of U.S. Pat. No.
3,784,907. Stated very briefly, the LSSD approach comprises a test
operation wherein certain desired logic-test patterns are serially
inputted and shifted to the appropriate latch locations when the unit is
operated in the "shift mode", so to speak, (i.e. by withholding the system
clock excitations and turning on the shifting clock to the unit). When
this is done, the latch states will provide the desired stimuli for the
testing of the related logic nets. Now, propagate the test patterns
through the nets by executing one or more steps of the "Function Mode"
operation (i.e., by exercising one or more system clock excitations). The
response pattern of the logic networks to the applied stimuli is now
captured by the system latches, in a known manner depending on certain
details of hardware design, often replacing the original inputted test
patterns. Then the system reverts to the shift-mode operation, outputting
the response patterns for examination and comparison with standard
patterns which should be present if the circuitry has operated properly.
The previous description of LSI circuitry testing problems presupposes that
the individual LSI chips have been manufactured on larger wafers,
subsequently "diced" and individually tested prior to assembly into
modules. The present state of the LSI fabrication technology is such that
full wafer integration of logic circuits is still unfeasible, mainly due
to three reasons, limitation of yield, limitation of field size in
high-resolution photolithography and the impracticability of realizing
economically a large number (105-106) of random-logic circuits as an
iterative array. Thus, LSI is still being limited to an area (a chip) much
smaller than that of a wafer, and current practice is to batch-fabricate
on a wafer a number of chips of the same type by "step-and-repeat"
techniques and then cut up the wafer into chips at the end of processing.
As far as the accept/reject testing of individual chips is concerned,
basically three approaches are conceivable. The first is to cut the wafer
into chips and then functional-test them individually. A second approach
is to do a coarse (maybe-good or maybe-no-good) test of the chips before
dicing the wafer and then to cut out and functional-test only those chips
which have been found to be "maybe-good". The third approach is to
functional-test the individual chips in-situ before dicing the wafer.
Obviously, the choice among these approaches depends on many factors. The
chip yield, the ease and cost of handling, the cost of test equipment, of
the individual tests, of dicing, etc. For instance, the second approach
above could be preferable to the first only if the chip yield is low and
the cost of introducing the coarse on-wafer test is lower than that of
dicing and individually coarse-testing the bad chips. On the other hand,
the third approach would be definitely superior to the first and second
approaches with respect to the ease and cost of handling, but it imposes
certain extreme requirements on the test equipment, making it
prohibitively costly and technically infeasible. These requirements and
the problems they present involve the following. There is great difficulty
in making good and reliable probing contacts onto a large number of pads
on the chip. This involves miniaturized-construction and space-limitation
problems. It is also difficult to connect the probing contacts to the
tester. Many if not all of these connections have to be high-quality,
suitable for matched pulse-signal transmission, so as to be usable for
functional tests. This aggravates the miniaturized-construction and space
limitation problems. Providing for step-and-repeat probing onto the
individual chips on the wafer is also a major problem. This involves very
high precision mechanical construction of the test equipment and thus high
initial and maintenance costs.
All of these problems are further aggravated in the case of chips built in,
for example, Josephson technology, since testing must be done with the
chips at liquid helium temperatures. Further, the art is continually
exploring ways to achieve higher circuit speeds. Consequently, the
situation often encountered is that the circuits under development and to
be functional-tested are much faster tnan the test equipment available.
The present invention provides a design approach and testing method which
circumvents these problems and will allow on-wafer testing of individual
chips to be done without necessitating expensive test equipment involving
high precision step-and-repeat mechanisms. The method should be applicable
to the testing of LSI logic chips fabricated in semiconductor or other
circuit technologies (e.g., Josephson). The basic concept is to utilize
chip configurations incorporating LSSD circuit design and so organize the
wafer that such LSSD circuitry incorporated in the chips can be utilized
for on-wafer testing.
There are a number of patents set forth in the "Background Art" section
illustrating various examples of chip/wafer structure wherein additional
circuitry is utilized on the wafer surrounding the actual chip core for
various chip interconnection and/or chip testing purposes. Individual
chips on such an array include certain minimal switching circuitry by
which row-column addressing of particular chips is possible whereby an
individual circuit may be selected by energizing appropriate row and
column address lines for applying tests from external circuitry and
accessing the results from a particular chip. However, none of the
disclosed prior-art structures utilizes chip-contained circuitry to form
an on-wafer and/or on-module configuration that actually allows the
functional testing of the chips to be done on-wafer or on-module.
Furthermore, with the increasing circuit densities and complexities in the
chip, limitation due to the relatively small number of I/O lines available
for testing purposes makes the provision for functional testing of the
chip more and more difficult.
It is accordingly a primary object of the present invention to provide an
arrangement and method which allows exhaustive functional-testing of
individual LSI chips to be done on-wafer.
It is another object of the present invention to provide an LSI chip and
wafer configuration which, using the LSSD testing circuitry incorporated
in the individual chip images and providing the proper inter-chip and I/O
connections on the wafer, makes the application of the said testing method
possible.
It is a further object of the invention to provide an arrangement and
method, with which the circuitry incorporated and utilized for the
on-wafer testing can subsequently be utilized also for on-module testing
where the chips may remain mounted in their respective subassemblies.
2. Background Art
The following patents are illustrative of the LSSD Testing Arrangements and
Organizations and should be referred to for detailed description of their
underlying principles. It should be understood that the present invention
does not claim any novelty in the use of any particular LSSD architecture
but only in the broad architectural concept of utilizing such circuitry
together with additional circuitry to facilitate on-wafer testing of LSI
chips.
U.S. Pat. No. 3,783,254 entitled "Level Sensitive Logic System",
application Ser. No. 297,543, filed Oct. 16, 1972, granted Jan. 1, 1974 to
E. B. Eichelberger and of common assignee.
U.S. Pat. No. 3,761,695 entitled "Method of Level Sensitive Testing a
Functional Logic System", application Ser. No. 298,087, filed Oct. 16,
1972, granted Sept. 25, 1973 to E. B. Eichelberger and of common assignee.
U.S. Pat. No. 3,784,907 entitled "Method of Propagation Delay Testing a
Functional Logic System", application Ser. No. 298,071, filed Oct. 16,
1972, granted Jan. 8, 1974 to E. B. Eichelberger and of common assignee.
The following list of patents is exemplary of prior-art approaches
utilizing the deposition of circuitry in the kerf areas between logic
chips on the wafer.
U.S. Pat. No. 3,781,683 entitled "Test Circuit Configuration for Integrated
Semiconductor Circuits and a Test System Containing Said Configuration",
application Ser. No. 129,429, filed Mar. 30, 1971, granted Dec. 25, 1973
to L. E. Freed and of common assignee.
U.S. Pat. No. 3,849,872 entitled "Contacting Integrated Circuit Chip
Terminals Through the Wafer Kerf," application Ser. No. 300,075, filed
Oct. 24, 1972, granted Nov. 26, 1974 to E. M. Hubacher of common assignee.
U.S. Pat. No. 3,913,072 entitled "Digital Integrated Circuits", application
Ser. No. 381,686, filed July 23, 1973, granted Oct. 14, 1975 to I. Catt.
Article entitled "Memory System Fabrication Using Laser Formed
Connections", by T. W. Cook and S. E. Schuster, IBM Technical Disclosure
Bulletin, Vol. 17, No. 1, June 1974, page 245.
DESCRIPTION OF THE DRAWINGS
FIGS. 1A through 1G illustrate the various possible circuit structures
which may be contained in an LSI Logic chip. The terminology used in these
figures is also used in the other drawings and the specification.
FIGS. 2A and 2B illustrate the gating of serial test-data output from chip
to chip for on-wafer testing.
FIGS. 3A through 3D illustrate the provision of supplementary latches and
gating of serial output and parallel inputs, in the cases of four
chip-circuitry structures and two chip-image-extension approaches.
FIGS. 4A through 4C illustrate a "self-sufficient" arrangement of using a
chip's latches to store test-data input and output for on-wafer testing.
FIG. 5 illustrates a "self-sufficient" arrangement in case of the chip
containing a mixture of circuit structures as shown in FIG. 1(g), with
cutaway and the deactivate approaches.
FIG. 6 illustrates a "self-sufficient" arrangement in case of the chip
containing a mixture of circuit structures as shown in FIG. 1(g), with the
extend-usage approach.
FIGS. 7A through 7C illustrate the "neighbor-assisted" arrangement of using
latches in an adjacent chip to store test-data inputs or test results for
on-wafer chip testing, with the cutaway and the deactivate approaches, for
circuitry shown in FIGS. 1B, 1C and 1D.
FIGS. 8A through 8C illustrate the "neighbor-assisted" arrangement of using
latches in an adjacent chip to store test-data inputs or test results for
on-wafer chip testing, with the extend-usage approach, for circuitry shown
in FIGS. 1B, 1C and 1D.
FIG. 9 is a summary of the number of "global" interchip connections needed
on the wafer in the cases of various arrangements and approaches.
FIGS. 10A through 10D comprise schematic diagrams showing the "global"
connections traversing a chip in the four illustrated arrangements and
approaches.
FIGS. 11A and 11B illustrate the connection of a chip-image array to the
contact pads on a wafer.
FIGS. 12A and 12B illustrate the linear and array method for connecting
chips with self-sufficient extend-usage design for on-module testing.
FIGS. 13A and 13B illustrate the linear and array method for connecting
chips with neighbor-assisted extend usage design for on-module testing.
FIGS. 14A and 14B provide a general summary of the schemes for the on-wafer
and on-module testing of chips respectively.
DISCLOSURE OF INVENTION
The present invention comprises two closely related concepts: (1) a special
chip-design approach to allow on-wafer testing, and (2) a method for using
the special chip design for on-wafer testing and subsequently (in the case
of the extend-usage approach) also for on-module testing of the chips.
Generally speaking, a logic chip may contain many circuits of different
types which in combination, form structures. Depending on whether an
information-retaining or an information-processing capability is involved,
circuit functions may be divided into two main categories: latches (L) and
combinatorial networks (CN). The various circuit structures which may be
encountered in a chip are shown in FIG. 1 as cases (a) through (g). These
are:
(a) L(=latches) alone,
(b) CN (=combinatorial networks) alone,
(c) L-CN structures,
(d) CN-L structures,
(e) L-CN-L (or L-CN-L-CN- . . . -L) structures,
(f) CN-L-CN (or CN-L-CN-L- . . . -CN) structures, or
(g) a mixture of the above.
In the following description, such circuit structures, when referred to,
will be called (a), (b), (c), (d), (e), (f) or (g)--as they are shown in
FIG. 1--for simplicity. As mentioned before, the on-wafer chip-testing
scheme being described relies on the utilization of LSSD provisions in the
chips. Thus the presence of some latches is being presumed. If a chip has
no latches in it, then latches will have to be provided in addition. Seen
from this respect, case (b) above (with CN alone) will be uneconomical and
unfavorable. Similarly, case (f) with CN-L-CN structures will be also
unfavorable, because the latches therein are not readily accessible across
the chip boundary and therefore are difficult to use for test purposes.
Thus, for economy and amenability to the test scheme of the present
invention, circuit structures which have latches with either their inputs
or outputs accessible across the chip boundary will be preferred. These
are the cases (a), (c) through (e), and case (g) provided it is a mixture
of cases (a), (c), (d) and (e).
The partitioning of circuitry into chips should be done, therefore, in such
a way that each chip type would, if possible, be equipped with some
latches either at the input or the output end of the chip. This is
desirable mainly for economy and for simplification of test procedures;
however, it does not necessarily constitute any prerequisite for using the
test scheme.
All latches which are provided on the chip should be so designed that they
can be operated also in the LSSD mode. This requires that the latches
should, besides their normal functional input and output connections, be
linked together in such a way that, when operated in the LSSD mode, they
form a shift-register chain so that information can be put into or taken
from any or all of them by serial shifting.
Seen from the testing point of view, case (a) with L alone may be
considered trivial, since it is already implied by the provision of LSSD;
from the on-wafer-testing point of view, however, the generation of
L-alone chips must be considered as a wasteful partitioning practice,
since it lets the potential usefulness of the latches for on-wafer testing
go unexploited. As already mentioned, case (b) is uneconomical, whereas
cases (c) and (d) are the preferred structure forms. Case (e) is actually
a concatenation of (a) with (c) or (d): it is acceptable as far as
on-wafer testing is concerned, but it should not exist too often,
otherwise it may be the result of an unfavorable partitioning
strategy--since, for a system which basically comprises a large number of
L-CN-L-CN- . . . chains, taking out the L-CN-L structure more than once
would unavoidably create the case (b) with CN alone, which will be
uneconomical. Case (f) is a concatenation of (b) with (c) or (d): it will
also bear the unfavorable consequence of (b)'s as being uneconomical, and
like (e), it will also be the result of a poor partitioning strategy,
since it will unnecessarily cause some chip to be case (a) with L alone,
which will be wasteful. Case (g) simply exemplifies that cases (a) through
(f), together with their respective advantages or disadvantages, are
allowed to coexist mixedly on a chip, which may cause some slight
complication in test procedures, but not necessarily an increase in the
overall testing time. The above-mentioned points will become self-evident
after the following exposition of the chip-testing scheme details.
There will now follow a discussion of extensions in the chip-image design
for on-wafer testing. In the following description, the expression
"chip-core' will be used to designate the amount of circuitry as allocated
to a chip by the partitioning of a system being implemented. The
expression "chip proper" will mean the content of a chip after dicing,
which then may or may not comprise additional circuits for test purposes.
"Chip image" will mean the image being actually used by step-and-repeat
photolithography to make an array of chips on the wafer. Obviously, in
physical size, the chip image is always at least slightly larger than the
chip proper; in functional content, however, the chip image may be larger
than or equal to the chip proper. (Thus, the expression "chip image" here
includes the normally-called kerf areas). In turn, the chip proper can be
larger than or equal to the chip core both in physical size and functional
content.
In order to make on-wafer testing of chips possible, the chip image should
be expanded to include additional gating circuits and connecting paths
among the chips. These additional circuits and paths will be called
`extras` in the following description.
Three alternative approaches are possible:
(A) "Cutaway" approach: The extras will be used for the purpose of on-wafer
testing of the chips only. After the testing, the chip-proper will be
diced and the extras (preferably to be placed in the kerf areas as much as
possible) will be cut off and discarded. Functionally: chip image>chip
proper.gtoreq.chip core.
(B) "Deactivate" approach: The extras will be retained in the chip-proper,
but will be left unused. The chip image can be so designed that the extras
be placed in the inactive areas of the chip proper (e.g., among the pads,
if possible). If necessary, some of the connections for the extras can be
scraped open to reduce the effects of loading or reflections, etc. In this
case, functionally: chip image>chip proper.gtoreq.chip core.
(C) "Extend-usage" approach: The extras will be retained on the
chips-proper, and will remain connected and be used for purposes beyond
the on-wafer testing of the chips. Here, functionally: chip image=chip
proper>chip core. One of the possible uses will be the on-module testing
of the chips. This is a unique feature, with a high potential for
providing a powerful tool for the diagnosis of a module populated with all
its chips soldered in place. This will be described in more detail later.
Closer consideration indicates that, as far as the wafer real-estate
utilization is concerned, there is actually little difference among the
three approaches: the primary difference will be that, with (A), the diced
chip size can be somewhat smaller (this usually, though, would not be an
important issue). As will be seen presently, all three approaches will
need additional connecting paths and gating circuits, and the approach (C)
will need additional I/O pads and gating circuits.
The first important extension in the chip-image design is the incorporation
of gating of the serial test-data output from the chips. The present
approach differs from the conventional LSSD concept in that, whereas it is
assumed there that the latches in a long shift-register chain, which may
encompass a large number of chips or modules or even the whole system, are
all in working order and therefore can be used for testing. The present
scheme must, on the contrary, suppose that probably many of these shift
register latches on the wafer may fail. A reasonable test strategy,
therefore, is to make the testability of any given one chip be dependent
upon the usability of as few other chips as possible. This implies that
not all the latches on the wafer, but only those in one or two chips at a
time, should be linked together to form the shift-register chain for LSSD
test-data input and output purposes. In other words, switching is needed
to configure the paths on the wafer in order to output only the test
results from the chip being tested.
FIG. 2 shows the basic principle of gating the chips' serial test-data
output for on-wafer testing. The shift outputs of the latches on the chips
of a row are fed through AND and OR gates, onto a test-data-out cascade
line or bus. (For semiconductor chips, the OR's can be DOT-OR's or the
AND-OR combinations can be tri-state output arrangements.) Obviously, this
test-data output switching will be needed in all the three (cutaway,
deactivate, and extend-usage) approaches. As will be seen later, it can be
arranged, if the number of wafer-contact pads allows it, that each row of
chips has a serial test-data output, so that the on-wafer chip testing can
be speeded up by testing multiple chips, one in each row, simultaneously.
With the serial test-data outputs from the chps being selectively
switchable, there is no need for switching also the serial test-data
inputs to the chips. A test pattern can be shifted into all chips at the
beginning of a test cycle: only the outputs of the chips under test (e.g.,
one in each row of chips) will be shifted out to be examined.
The second essential extension in the chip-image design is the provision,
if necessary, of supplementary latches on each chip to accomplish the
temporary storage of data (serial-input test patterns and test results to
be shifted out) for the on-wafer testing.
Basically, the functional test of a logic chip comprises a number of steps,
each of which consists in feeding the CN (combinational networks) of the
chip with a test-sensitive input pattern and then observing the networks'
output pattern after a single logic cycle. The input and output patterns
have to be stored in latches at the beginning and end of the test cycle.
By suitably arranging for the connections, one set of latches on the chip
can be used to store either the input or the output, or both (first the
input, then the output). Thus, at least one set of latches will be needed.
If the combinatorial networks on the chip have N.sub.i input and N.sub.o
output bits or lines, then obviously the set must comprise N.sub.io
latches, where N.sub.io =N.sub.i N.sub.o =the larger one of N.sub.i and
N.sub.o being the symbol for "ceiling"). If there are N.sub.L latches in
the circuits on the chip, and if N.sub.L <N.sub.io, then N.sub.L 1
(=N.sub.io -N.sub.L) latches will have to be furnished additionally in
order that the total number of latches provided in the chip will be
sufficient for storing, one after the other, the N.sub.i input and N.sub.o
output bits. As is shown in FIG. 3, N.sub.L, is 0 in the case of (a) with
L alone in the chip core; is N.sub.io in the case of (b) with CN alone; is
0 if N.sub.i .gtoreq.N.sub.o, or (N.sub.o -N.sub.i) if N.sub.i <N.sub.o,
in case of (c) with L-CN; and is 0 if N.sub.i .ltoreq.N.sub.o, or (N.sub.i
-N.sub.o) if N.sub.1 >N.sub.o, in the case of (d) with CN-L. This
indicates that the structure (a) with L alone is wasteful with respect to
on-wafer test, since the L could have been used by some CN, whereas the
structure (b) with CN alone, besides being incompatible with the LSSD
concept on the chip basis, will be uneconomical for the on-wafer
chip-testing scheme because N.sub.L, in this case will be largest. This
also indicates that, for a system in which the combinatorial networks
mostly have more inputs than outputs (N.sub.i <N.sub.o), partitioning into
L-CN structured chips will be preferable if the on-wafer testing scheme is
to be used; on the other hand, if most of the networks have more outputs
than inputs (N.sub.o <N.sub.i), then partitioning into CN-L structures
will be more favorable. As mentioned earlier, cases (e) and (f) can be
considered as a concatenation of (a) and (b), respectively, with (c) or
(d): the provision of supplementary latches in these cases can be treated
accordingly. In the case of (g) with a mixture of different circuit
structures, some "sharing" of the latches on the chip is possible, in
that, when latches pertaining to a circuit structure have surplus input or
output capacities which are not utilized for test within that structure,
they can be used as supplementary latches for other structures. This is
illustrated in FIGS. 5 and 6.
The third essential extension in the chip-image design is the incorporation
of gating of the parallel inputs to the chip core, in order to render the
chip operable either in a test mode (TM) or in the normal operation mode
(OM). Obviously, this gating will be needed mainly in the extend-usage
approach, since in the cutaway and deactivate approaches (where the test
mode will be extinct after the chip dicing), irreversible "switching" can
be realized by cutting. In the right-hand (extend-usage approach) column
in FIG. 3, gating of the parallel inputs to the chip core as needed is
shown. It is seen that in the case of (a) with L alone, no gating of the
inputs to the L will be needed (an indication that the potential
usefulness of L for test purposes is left unexploited); in the case of (c)
with L-CN structure, the gating is as the input to L; in the case of (b)
with CN alone and of (d) with CN-L, the gating is at the input to CN.
Compared to the cutaway and deactivate approaches, the extend-usage
approach will need more I/O pads at the chip boundary: .DELTA.n.sub.p
=(N.sub.io +4x), (N.sub.o +3x-1) and (N.sub.i +N.sub.L,+3x-1) in the case
of (b), (c) and (d) respectively, with x=1 for parallel and 2 for serial
feed. (In the case of "self-sufficient" arrangement to be described below,
this .DELTA.n.sub.p will be reduced to 4x, (3x-1) and (3x-1)
respectively.)
Another essential extension in the chip-image design is the incorporation
of in-chip and/or interchip connections to allow the chips to be tested
while together on a wafer. This section will describe mainly what
connections there should be. How they will be used will be explained
later, in the `Best Mode` section, when the method of testing will be
described. Basically there are two arrangements possible. In the first,
the latches of a chip will be used to store both its test-data inputs and
later also its test results. This will be called the "self-sufficient"
arrangement. In the second, the latches of a chip will be used to store
either the test-data inputs or the test results, but not both. For the
results or the inputs, then, the latches of a neighboring chip will be
used in addition. This will be called the "neighbor-assisted" arrangement.
As will be seen, both of these arrangements have their advantages and
disadvantages. Essentially, the self-sufficient arrangement may be more
suitable for the extend-usage approach, whereas the neighbor-assisted
could be used for all three approaches. The self-sufficient arrangement
consists essentially in connecting the parallel ouputs of each chip back
to the test-mode-gated parallel inputs of the same chip. FIGS. 4 to 6 show
these connections in the cases (b), (c), (d) and (g) for the cutaway and
deactivate approaches and for the extend-usage approach. For the former,
the loop-back lines (which, together with the other extras, should
preferably be placed as much in areas outside the chip proper as possible)
will be cut off or severed; for the latter, these lines will be retained
and will be used for post-dicing test purposes.
The self-sufficient arrangement has the advantage of being self-contained,
in that it does not rely on the usability of other chips. This means: each
chip will be testable by itself. Malfunctioning of latches on one chip
will only make that chip untestable and unusable, but will not affect the
testability of other chips. Also, with the self-sufficient arrangement,
the extend-usage approach will use only a few more I/O pads than the
cutaway and deactivate approaches (compare FIG. 4 and FIG. 8).
While the second point above tend | | |
