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CROSS-REFERENCE TO RELATED APPLICATIONS
Reference is hereby made to the following copending patent applications,
filed on even date herewith and assigned to the NCR Corporation; Symbol
Processing System, Ser. No. 043,971, by Blanford et al.; Slot Scanning
System, Ser. No. 043,928, by S. Naseem et al.; Topography for I.C. Pattern
Recognition Array, Ser. No. 043,929; by Orgill et al. and Topography for
I.C. Frame Control Chip, Ser. No. 043,930, by Gardner et al.
BACKGROUND OF THE INVENTION
The present invention relates to a novel method and means for decoding a
high density multiple bar code from a record medium at a high rate of
speed and more particularly, relates to a NMOS/LSI chip which receives
electrical signals generated as the result of scanning a symbol or a label
on which is located a multiple bar code such as the Universal Product Code
(UPC) and provides signals identifying the unique characters represented
by the scanned bar code.
The use of bar coded symbols or labels intended to be read by optical
scanning equipment as a means for identifying new data useful in
processing items sold in the retail industry has been widely accepted to
the point that a particular bar code known as the Universal Product Code
(UPC) has been established as the industry standard for the grocery and
other related retail industries. In the multiple bar code, such as the
UPC, each decimal number or character is represented by two pairs of
vertical bars and spaces within a 7-bit pattern wherein a binary 1 bit
represents a dark module or bar of a predetermined width and a binary 0
represents a light module or space. Thus, the decimal or character 1 may
be represented in the UPC code by the 7-bit pattern 0011001. In keeping
with the format, the decimal 1 would be comprised of an initial space of a
2-bit width, followed by a 2-bit wide bar, another 2-bit space and a 1-bit
wide bar. For each character or decimal of the system there are two bars
and two spaces which have a total width of seven modules or bits. The
width of each of the bars or spaces which comprise a character may be 1,
2, 3 or 4 modules wide as long as the sum of the bars and spaces is seven
bits or modules wide.
A multiple bar code, such as the UPC, is normally read by an optical
scanner which may take the form of a hand-held wand or a scanner mechanism
located in a check-out counter. The optical scanner will scan the bar code
pattern and generate signals representing the bars and space for
transmission to the processing apparatus which determines the character
represented by the bar code pattern.
Prior optical readers generally store the electrical signals generated as a
result of scanning the bar code pattern until the accumulated signals
stored are sufficient to allow the processing apparatus to initiate a
recognition operation to determine the character represented by the
scanned bar code pattern. Because of the speed in which the scanning
operation is performed, the cost of the prior optical readers in
processing the electrical signals has been unduly expensive, which in many
instances has prevented the readers from reaching the marketplace. It is
therefore the principal object of this invention to provide a low-cost
optical character reader. It is another object of this invention to
provide a low-cost optical character reader system which operates at a
relatively high rate of speed without a loss of recognition efficiency. It
is the further object of this invention to provide a recognition system
embodied in an NMOS/LSI chip.
SUMMARY OF THE INVENTION
In order to carry out these objects, there is provided a high speed optical
character reader system which includes a slot scanner mechanism for
scanning the bar pattern of a symbol or coded tag which bar pattern
includes a plurality of bars and spaces and outputting binary signals
representing the time intervals between the edges of bar-to-space and
space-to-bar. The binary signals representing the time intervals together
with a second binary signal indicating the presence of a bar or space are
transmitted to an NMOS/LSI chip which includes a plurality of binary
adders, comparators, shift registers and discrete logic elements for
decoding in parallel each time interval received to output in parallel a
4-bit binary bit hexadecimal number which may represent a decimal
character, the margin or the centerband of the symbol, together with
binary bits indicating whether the decimal character represents a bar or
space, the direction in which the scanning sequence occurred, and whether
the decimal character in the hexadecimal number is a valid or invalid
character. Other features and advantages of the present invention will be
apparent from the preferred embodiment hereinafter set forth and
illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a graphical representation of a symbol or coded label such as a
UPC coded symbol;
FIG. 2 is a graphical representation of the character structure of the UPC
symbol;
FIG. 3 is a table showing the code structure of the UPC symbol character;
FIGS. 4A and 4B are graphical representations of the bar pattern and the
transformed binary symmetrical signal;
FIG. 5 is a graphical representation of a bar code illustrating the
dimensional relationships utilized in the present recognition system;
FIG. 6 is a block diagram of the various arrays which comprise the pattern
recognition and scanning system;
FIG. 7 is a block diagram of one embodiment of the present invention
wherein a recognition chip receives the output signals of the scanner and
generates decoded data representing the bar code scanned;
FIGS. 8A-8L inclusive taken together disclose the logic circuits for
generating signals representing characteristics of each interval scanned
by the scanner unit;
FIG. 9 is a diagram showing the manner in which FIGS. 8A-8L inclusive are
arranged with respect to each other to form the logic circuits;
FIGS. 10A-10C inclusive taken together disclose the logic circuits for
generating signals used in recognizing the character represented by the
bar code scanned by the scanner unit;
FIG. 11 is a diagram showing the manner in which FIGS. 10A-10C inclusive
are arranged with respect to each other to form the logic circuits;
FIG. 12 is a diagram showing the logic circuits for decoding the characters
1 and 7;
FIG. 13 is a diagram showing the logic circuit for decoding the characters
2 and 8;
FIG. 14 is a diagram showing the logic circuits for decoding the characters
9 and 3-6 inclusive;
FIG. 15 is a diagram showing the logic circuits for encoding the
hexadecimal signals;
FIGS. 16-20 inclusive contain equations of the logic terms employed in the
present invention.
DESCRIPTION OF THE PRESENT EMBODIMENT
Referring now to FIG. 1, there is shown a graphical representation of a UPC
symbol or coded label. The UPC symbol is made up of a series of light and
dark parallel bars which comprise twelve characters. Among the twelve
characters, two characters are the industry code and a modulo check
character and the remaining ten characters are the main code representing
data associated with a merchandise item. As shown in FIG. 1, included is a
readable number printed in OCR-B font. In addition to the series of light
and dark parallel bars, the UPC symbol includes spaces on both sides which
are referred to as the left and right margins. Other characteristics of
the UPC symbol include the following:
(1) The overall shape of the symbol is rectangular;
(2) Each character of a UPC code is represented by two dark bars and two
light spaces;
(3) Each character is comprised of seven equal data elements called
modules;
(4) Each module can be light or dark;
(5) Each bar may be composed of 1, 2, 3, or 4 dark modules. Light spaces
may also be composed of 1, 2, 3, or 4 modules;
(6) Each character is independent;
(7) The right-most character of the symbol is a modulo check character
while the left-most digit of the symbol indicates a system in which this
symbol is encoded;
(8) The size of the UPC symbol is variable, that is, it may be large or
small without affecting its readability. The UPC symbol may consist of
only six characters having the same arrangement as shown in FIG. 1;
(9) The series of light and dark parallel bars are separated from the
margins on each side by left and right guard bar patterns and includes a
center band pattern located at the center of the UPC symbol.
Referring now to FIG. 2, there is shown a graphical representation of the
character structure of the UPC symbol. As shown, each encoded UPC
character is made up of two dark bars and two light spaces each composed
of a differing number of modules. By assigning a 1 which corresponds to
the black module and a 0 to a white module, the lefthand character
represents (0101111) which denotes the character 6 and the right hand
character represents (0001101) which denotes the character 0. The
structure of the character code is not uniquely determined by each
character, but is different according to which side of the center band
pattern the character is located on. It is thus arranged that the light
modules and the black modules are reversed as the character is located on
the right or left sides, and as a result an odd number of black modules is
included in each character code on the left hand side and an even number
of black modules is included in each character code on the right hand side
as indicated in FIG. 3. This parity relation provides information for
determining the read-out direction of the codes. With this arrangement,
the left-hand characters always start with light bars and the right-hand
characters always start with dark bars (reading left to right). The whole
structure of the character codes is as shown in the Table in FIG. 3. It
should be noted that the number of dark modules in the left side digit is
always 3 or 5 while the number is always 2 or 4 for the right hand digit.
These characteristics are used as a parity check. The left side digits
have odd parity while the right side digits have even parity.
After a character is scanned, each module is assigned a binary value. Thus,
as shown in FIGS. 4A and 4B, scanning of the modules in the direction as
noted, a binary 1 signal is generated upon the sensing of a black bar,
while a binary 0 signal is generated upon the sensing of a light bar or
space. Because of problems in printing, it is uncommon for the width of
the light bar and the black bar to be of the ideal value. Therefore, in
decoding the UPC symbol, this condition must be taken into consideration.
In addition, the tolerances for a UPC symbol or tag are larger for the
space that starts or ends a character. Because of the print condition of
the bar and space alluded to above, it has been found that the dimension
tolerances between similar edges are better than between dissimilar edges,
that is, measuring the distance between trailing edges of adjacent bars
and spaces or measuring the distance between the leading edges of adjacent
bars and spaces produces data which gives high recognition efficiency to
the system.
Referring now to FIG. 5, there is illustrated the present method for
recognizing the characters represented by the pattern of the UPC bar code
as shown in FIG. 1. As previously described, each character comprises two
dark bars and two white bars or spaces. Representing each bar and space as
an interval, it will be seen that each character is composed of four
intervals, where each interval is composed of the same background, either
dark or white. To represent the most recent interval that has been sensed
by the scanner, the designation I.sub.N is used with the designation
V.sub.N representing the bar for that interval. The designation I.sub.N is
an 11 bit binary number generated in a manner to be described hereinafter.
To designate the interval preceding the current interval, the notation
I.sub.N-1 and V.sub.N-1 is used. For the interval before that, the
notation I.sub.N-2 and V.sub.N-2 is used and so on. The sum of the four
consecutive intervals scanned by the scanner is shown in FIG. 5 by the
notation S.sub.N where S.sub.N equals I.sub.N plus I.sub.N-1 plus
I.sub.N-2 and I.sub.N-3. For each interval scanned, the system examines
the three preceding scanned intervals together with the current scanned
interval and assigns a hexadecimal value. Each interval that is scanned is
then classified as a bar (binary 1) or a space (binary 0). If V.sub.N is a
binary 1 (bar), then I.sub.N +I.sub.N-1 and I.sub.N-1 +I.sub.N-2 are
compared to one half S.sub.N, 23/64 S.sub.N and 41/64 S.sub.N. From this
comparison two sets of weights can be found. Each of these weights will be
either 2, 3, 4 or 5. From these weights the system will determine if a
character is odd or even parity. Further utilizing these weights, the
system will establish the characters 0, 3, 4, 5, 6, and 9. However, two
sets of ambiguous characters are found. The characters 1 and 7 are
ambiguous, that is, both have the same apparent configuration, and also
the characters 2 and 8. To distinguish between the characters 2 and 8
requires finding if the interval I.sub.N-1 of each character is greater
than the interval I.sub.N-2. If it is greater, the character is 2. Odd
parity 1 and 7 can be separated by determining if intervals I.sub.N is
greater than the interval I.sub.N-1. If in this case it is greater, the
character is a 1. Even parity 1 and 7 requires that the term 21/32
I.sub.N-2 is greater than I.sub.N-1. In this latter case, if the term is
greater, the character is a 1. In all of these cases, the single intervals
were all used to determine the ambiguous characters.
Upon the scanning of each interval, the system will sum the three previous
intervals together with the current scanned interval and then compare the
sum of those four intervals S.sub.N (FIG. 5) with the previous sum S.sub.N
generated to determine if they are equal within a predetermined limit.
Thus, a signal EQUAL indicating equality will be generated if 27/32
S.sub.N is less than S.sub.N-4 and S.sub.N is greater than 27/32 S.sub.N-4
and no error is detected. An error condition exists where the width of an
interval exceeds the predetermined count.
Referring to FIG. 1, it will be seen that the bar code symbol has left and
right margins and the center band portion of the code. When scanning from
left to right as viewed in FIG. 1, the left margin will be characterized
as the in margin while the right margin will be characterized as the out
margin. Similarly, the left portion of the center band will be
characterized as the in center band and the right binary bits generated
for use in recognizing the character contained in the hexadecimal number
being outputted at that time. As pointed out previously, each interval
scanned will result in the outputting of a hexadecimal number which
contains four binary-coded decimal (BCD) bits with only a portion of the
hexadecimal numbers outputted being valid.
Referring now to FIG. 6 there is shown a block diagram of the character
recognition system in which the present embodiment is utilized including a
slot scanner 20 which causes a laser beam to be reflected to produce a
scanned portion above and in front of a slot or opening adjacent the
laser. If a UPC symbol or tag is placed such that the laser beam crosses
the tag thereby reflecting the light from the bars and spaces which
compose the UPC tag, a photodetector receiving the reflected light will
transform the reflected light into an electrical signal. A video amplifier
(not shown) located in the scanning unit generates, in response to the
generated electrical signals, digital pulses STV (Set Video) indicating a
space-to-bar transition and RTV (Reset Video) indicating a bar-to-space
transition. The time interval between these pulses is a function of the
width of the bar or space. The pulse width of the signals STV and RTV can
be from 25 ns. to 2 us sec. Valid signals alternate are never closer
together than 350 ns. This means that following a valid STV or RTV,
multiple pulses may occur during this 350 ms. time period.
These time intervals are transmitted to a counter control chip 22 (FIG. 6)
in which the intervals are converted to a binary number by an interval
counter and then transmitted to a FIFO (First-In, First-Out) IC array. The
FIFO time averages the time between intervals to an acceptable period.
Either of the signals STV and RTV will stop the interval counter and cause
that interval count along with the state of a VIDEO flip-flop (not shown)
to be stored in a FIFO shift register (not shown). The VIDEO flip-flop
will be true for a bar. The interval counter at this point is reset and
the next interval count is started. If the output of the interval counter
is greater than 1280 counts (32 us.), an overflow condition is created. In
the overflow state, every 800 ns. of the count of 1280 and the last state
of the VIDEO flip-flop will be loaded into the FIFO shift register. The
occurrence of the next STV or RTV signal will result in the loading of an
additional 1280 count into the FIFO shift register. This condition will
cause an error signal to be generated which, as will be described more
fully hereinafter, will be sensed by the system at this time. Using this
error signal, the system will disregard the data that is being generated
by the slot scanner unit 20 and the counter control chip 22. The data
contained in the FIFO shift register located in the counter control chip
22 will be outputted to a decoder chip 24 which is the subject of the
present application under the control of clock pulses generated by a 40
Mhz. oscillator 26. The FIFO shift register will output 11 bits of binary
data representing the width of the interval being scanned over bus 23
(FIG. 6) together with a VIDEO signal indicating whether the interval is a
bar or a space. Also outputted from the counter control chip 22 to the
decoder chip 24 are clock pulses CLK. For a more detailed disclosure of
the counter control unit 22, reference should be made to the previously
cited co-pending application of Naseem et al., Ser. No. 043,928.
The decoder chip 24 (FIG. 6) contains a number of binary adders,
comparators, shift registers and discrete logic elements which are used to
decode the data being scanned by the slot scanner unit 20. The decoder
chip 24 will output a hexadecimal number which includes four BCD bits
representing a decimal character in addition to indicating margins, center
bands and error. Three additional binary bits are outputted by the decoder
chip 24 which represent the signal MARK to indicate the interval is a bar
or a space, the signal EQUAL indicating that the current interval taken
together with the three previous intervals are either equal or not equal
in width to the previous four intervals and the signal PARITY indicating
that the interval is odd parity if true or even parity if false, thereby
locating the interval on the left or right side of the center band.
The output signals from the decoder chip 24 are transmitted to a frame
control chip 28 (FIG. 6) which separates the valid data from the invalid
data being outputted by the decoder chip 24. The frame control chip 28
filters out this valid data by checking for framing characters, that is,
in and out margins, in and out center bands, and character equality to
identify the valid characters being decoded by the decoder chip 24. A good
segment of valid data is then transmitted over bus 29 to a microprocessor
chip 30 for further processing. The frame control chip 28 functions also
as a communication adapter for transmitting data to be sent from the
microprocessor through an interface adapter 32 to a host terminal 34 over
bus 33. The microprocessor chip 30 monitors photodetectors in the slot
scanner unit 20 to determine when an item is in position to be read by the
slot scanner. This data is transmitted to the microprocessor chip 30 over
a bus 36 coupled to a scanner control unit 38. Upon receiving the required
control signals, the microprocessor will then start monitoring the frame
control chip 28 for information. The microprocessor does correlation
analysis and modulo ten check to determine if it has a valid tag. Once a
valid tag is assembled, the data is transmitted to the host terminal
through the interface adapter 32. Reference should be made to the
previously cited co-pending applications of Blanford et al. Ser. No.
043,971 and Gardner et al., Ser. No. 043,930 for a full disclosure of
control chip 28, Orgill et al., Ser. No. 043,929 for a full disclosure of
the decoder chip 24 and Naseem et al., Ser. No. 043,928 for a full
disclosure of the microprocessor chip 30, each assigned to the present
assignee of the application, which disclosures are fully incorporated into
this application by reference.
Referring now to FIG. 7, there is shown a block diagram of the logic
circuits employed in the present embodiment for generating binary signals
representing the terms mark, equal, parity and a hexadecimal number which
may represent the interval as one of, or a part of a 9 decimal character,
the in center band, the out center band, the in margin or the out margin.
As previously described, the counter control chip 22 (FIG. 6) will
continually output binary data representing the width of the interval
being scanned by the slot scanner unit 20 (FIG. 6). This binary data is in
the form of an 11 bit wide binary word which is transmitted over bus 23
(FIG. 6) to the decoder chip 24. Also outputted at this time is a clock
pulse CLK which, as shown in FIG. 7, is transmitted through a delay
circuit 40 which delays the clock pulse a predetermined number of clock
times so that the output pulse from the delay circuit 40 will correspond
to the output of the logic circuits shown in FIG. 7 as a result of
processing the interval which was generated with the clock pulse in the
counter control chip 22. The delayed clock pulse designated MARK
identifies whether the interval processed by the logic circuits was a
space (binary 0) or a bar (binary 1). In the present embodiment, the delay
is 12 clock pulses.
As will be described more fully hereinafter, the interval being outputted
by the counter control unit 22 (FIG. 6) is transmitted to a latch member
104 (FIG. 8A) whose output will appear on bus 42 (FIG. 7). The current
interval segment designated I.sub.N is transmitted over the 11 bit wide
bus 42 to a delay circuit 44 on whose output at this time will appear the
previous interval I.sub.N-1. This latter term is transmitted over bus 46
to the summing circuit 48 which adds the current interval I.sub.N with the
previous interval I.sub.N-1 to output over bus 50 the sum of the two
consecutive intervals I.sub.N +I.sub.N-1. This latter term is transmitted
to a two clock pulse delay circuit 52 on whose output appears the sum of
the third and fourth previous intervals I.sub.N-2 +I.sub.N-3 which term is
transmitted over bus 54 to a summing circuit 56 to be added with the term
I.sub.N +I.sub.N-1, the summing circuit 56 outputting over bus 58 the term
S.sub.N which is the sum of the last four intervals scanned by the
scanning unit 20 (FIG. 6). The sum S.sub.N is then compared in the
comparator circuit 60 with the sum S.sub.N of the previous four intervals
to determine if they are equal. If they are, the character being outputted
at this time by the logic circuit is valid. If not, the character is not
valid. Since the logic circuits of FIG. 7 will output a character upon
receiving the 11 binary bits of data representing the width of each
interval, the binary bit representing the signal EQUAL and appearing on
the output line 61 of the comparator circuit 60 designates whether the
character is valid (binary 1) or invalid (binary 0).
The sum of the two intevals I.sub.N +I.sub.N-1 being outputted over bus 50
by the summing circuit 48 is also transmitted to a comparator circuit 62
which also receives over bus 58 the sum S.sub.N of the last four intervals
to output over bus 64 data which is transmitted to a decoder circuit 66
which decodes the input data to generate over line 68 a bit indicating odd
or even parity. The decoder circuit 66 will also output over line 70 four
BCD bits which are transmitted to an encoder circuit 72 which outputs a
hexadecimal number which may represent one of the decimal characters 0-9
based upon the data transmitted to the encoder circuit 72 from the decoder
circuit 66. The output data from the comparator circuit 62 is also
transmitted over the bus 64 to a center band logic circuit 74 which will
output over lines 76, 77 binary bits indicating whether the interval
corresponds to the in center band or the out center band which binary bits
are transmitted to the encoder circuit 72 for inclusion in the hexadecimal
number output. The sum of the two previous intervals I.sub.N +I.sub.N-1 is
also transmitted over bus 50 to a margin logic circuit 78 which will
output over lines 80, 81 binary bits designating the interval as part of
the in margin or the out margin, which binary bits are transmitted to the
encoder logic circuit 72 for inclusion in the hexadecimal number being
outputted from the encoder circuit. Thus, the logic circuitry of the
decoder chip 24 (FIG. 6) receives binary data bits representing the width
of the intervals scanned plus a bit indicating a bar or space from the
counter control chip 22 and decodes the data to output hexidecimal numbers
which represent a decimal character, together with other characteristics
of the interval for use by the system in recognizing the characters
represented by the bar code scanned by the slot scanner unit 20.
Referring now to FIGS. 8A-8L inclusive, arranged in the manner as shown in
FIG. 9, there is disclosed logic circuits for generating signals
representing characteristics of the intervals being scanned by the slot
scanner unit 20 (FIG. 6). Each interval received over bus 23 by the
decoder chip 24 is combined with the three previous intervals scanned and
then decoded into a 4-bit binary character. The width of each combined
four intervals is compared with the previous four intervals to determine
character equality. The characters are equal if the character lengths are
within eighty-five percent of each other. Each interval is processed to
determine if it is a part of a margin or part of a center band pattern. In
addition, the parity of the interval is determined. In addition, the logic
circuits checked for error conditions. Each of these operations are
carried out asynchronously in a manner that will now be described.
In the following discussion of the present embodiment, reference will be
made to the logic equations shown in FIGS. 16-20 inclusive, which
equations cover the logic circuits to be described. Referring now to FIG.
8A, there is shown in block form a portion of the counter control unit 22
(FIG. 6) which includes high-speed logic 88 receiving the 40 Mhz. clock
pulse from the oscillator 26 (FIG. 6) and the video signals RTV and STV,
each representing the edge of an interval scanned. The logic 88 will
output over bus 90 a 12 bit binary word representing the interval count,
which in the present embodiment has a minimum value of 350 nanoseconds.
Because of the high speed with which the system operates, the logic 88
includes a Johnson counter (not shown) which is preset to a predetermined
time interval and is operated to count the width of the interval after
allowing the previous interval count to be outputted into the decoder chip
24 (FIG. 6). The logic 88 will output a 12 bit word which includes an 11
bit binary word over bus 90 (FIG. 8A) representing the interval count, a
VIDEO bit over line 92 which is high if the interval is a bar and low if
it is a space. The logic 88 also outputs a clock pulse over line 94 which
clocks the binary word through a FIFO storage unit 96 which in turn
outputs in sequential order the 11 bit interval count over bus 23, the
VIDEO signal over line 100 and the clock pulse over line 102 to a latch
member 104 located in the decoder chip 24 (FIG. 6). The latch 104 will
output over line 108 the video signal at a clock pulse of 350 nanoseconds,
the pulse being designated VID0. The video clock pulse VID0 is transmitted
over line 108 to a plurality of shift registers 110-122 inclusive (FIG.
8B) which are arranged in series. Each shift register will produce a one
clock pulse delay whose output pulses are designated VIDl-VIDll inclusive
and which are used to clock the intervals through the logic circuits in a
manner that will now be described. The output clock pulse from the shift
register 132 is designated as the signal MARK which is used to identify
the binary character outputted by the decoder chip 24 upon receiving each
11 bit binary word representing the interval count from the FIFO 96.
Reference should be made to the previously cited co-pending application of
Naseem et al., Ser. No. 043,928, for a complete disclosure of the Johnson
counter and the logic 88.
The latch 104 will also output over the bus 106, which is designated as the
A bus, the 11 bit binary word representing the current interval count
which, as previously described, is designated as I.sub.N. The interval
count is then transmitted to the various logic blocks hereinafter
described which combine the current interval I.sub.N with the previous
three intervals scanned and then compares the sum of those four intervals
with the previous four intervals to generate a signal signifying whether
they are equal or not. In addition, the logic will generate a four bit
binary word representing a character as a result of receiving the interval
count I.sub.N. As will be described more fully hereinafter, only a portion
of the binary characters generated by the decoder chip 24 are valid.
The current interval count I.sub.N is transmitted over the A bus 106 to one
input of a comparator 136 (FIG. 8A). The interval I.sub.N is also
transmitted to a shift register 138 (FIG. 8A) which delays the interval
count one clock pulse such that appearing at this time on its output will
be the previous interval count I.sub.N-1. Each functional block disclosed
in the logic circuits other than the logic functional elements will delay
its input count one clock pulse. Thus, the interval count I.sub.N-1
appearing on the output of the shift register 138 is transmitted over a B
bus 140 to the other input of the comparator 136 whose output signal
appearing on line 142 will be high if the interval count I.sub.N-1 is
greater than the previous interval count I.sub.N-2 which signal is
designated as ambiguous (AMB) and is transmitted over line 142 to a seven
clock pulse delay shift register 144 (FIG. 8B). The output signal of the
shift register 144 designated as AMB 71 is transmitted over line 146 to a
portion of a logic circuit to be described hereinafter which determines
whether the character represented by the interval count is an ambiguous
character. The signal AMB 71 is also transmitted through a shift register
148 whose output signal AMB 82 is transmitted over line 150 in a similar
manner as that of the signal AMB 71 for use in determining the ambiguity
of the character represented by the interval count in a manner that will
be described more fully hereinafter. The output signal AMB 82 of the shift
register 148 is also transmitted through a shift register 152 whose output
signal I.sub.N-10 >I.sub.N-11 designated AMB 17 is transmitted over line
154 for use in a manner similar to that of the signals AMB 71 and AMB 82.
As will be described more fully hereinafter, the signal AMB 71 generated
in accordance with equation (2) of FIG. 16 while the signal AMB 17
generated in accordance with the equation (4) of FIG. 16, both signals
being used to distinguish between the ambiguous characters 1 and 7 (FIG.
12). The signal AMB 82 generated in accordance with the equation (3) of
FIG. 16 is used to distinguish between the ambiguous characters 2 and 8
(FIG. 13).
In addition to the signals AMB 71 and AMB 17, a third signal AMBE (FIG. 8E)
is generated in accordance with equation (5) of FIG. 16 for use in
distinguishing between the ambiguous characters 1 and 7 (FIG. 12) when
there is even parity. As shown in FIG. 8A, the 11 bit wide interval count
I.sub.N transmitted in parallel over the A bus 106 is coupled to a
multiplexer 158 (FIG. 8B) while the 11 bit wide interval count I.sub.N-1
transmitted over the B bus 140 is coupled to a second multiplexer 160.
Both multiplexers 158 and 160 are controlled by the clock pulse VID0 which
is transmitted over line 109 (FIG. 8A and 8B) to one side of the
multiplexers 158 and 160 and over line 162 and to the other side of the
multiplexers 158 and 160 through an inverter 164 and over line 166. Upon
the occurrence of the clock pulse VID0 the multiplexer 158 will transmit
the 11 bit wide interval I.sub.N over a BA bus 168 to a three clock pulse
delay shift register 170 which outputs the interval count over a AJ bus
172 (FIGS. 8B, 8D and 8E) to one input of the comparator 174 (FIG. 8E).
When the clock pulse VID0 goes low, the interval count I.sub.N-1 is
transmitted over the B bus 140 (FIG. 8A) to the multiplexer 160 (FIG. 8B)
and onto the BA bus 168 for transmission to the comparator 174 in the
manner described above. The other input to the comparator 174 receives an
interval count developed in the following manner.
The interval count I.sub.N transmitted over the A bus 106 (FIG. 8C) is
coupled to the multiplexer 176 while the interval count I.sub.N-1
transmitted over the B bus 140 is coupled to a second multiplexer 178.
Both the multiplexers 176 and 178 are controlled by the clock pulse VID0
applied over lines 109 and 180 and through the inverter 182 over line 184
to the multiplexers 176 and 178 in the same manner as that of the
multiplexers 158 and 160 described previously. Upon the occurrence of the
clock pulse VID0 being high, the interval count I.sub.N appearing on the A
bus 106 is coupled to an AB bus 186 by the multiplexer 176. The interval
count I.sub.N is transmitted over the AB bus 186 (FIG. 8D) to a shift
register 188 which will delay the interval count one clock pulse and
output the delayed interval count I.sub.N-1 over the AF bus 190 to a
second shift register 192 which delays the interval count a second clock
pulse which interval count I.sub.N-2 is then transmitted over the AG bus
194 (FIGS. 8D and 8E) to one input of an adder 196 (FIG. 8E).
The interval count appearing on the AB bus 186 (FIG. 8D) is also
transmitted to one input of an adder 198 (FIG. 8D) whose other input
receives the same interval count minus the two least significant bits ABQ
and ABl of which the bit ABl is coupled to the carry input of the adder
198 which outputs an interval count which is 11/4 the count of the
interval count appearing on the AB bus 186. Dropping of the two least
significant bits in AB bus 186 reduces the i | | |
