A universal register which consists of a plurality of identical emitter coupled logic (ECL) bit slices and auxiliary ECL gates adapted for fabrication on a single large scale integration (LSI) chip. Each bit slice is comprised of a master-slave flip-flop (a master latch circuit and a slave latch circuit) and an output control network which is driven by the flip-flop. Each of the latch circuits and the output control network comprises a single stage (unit propagation delay), two decision level cascode ECL circuit. The output control network selectively supplies either the Q or the Q output signal from the flip-flop or a logic zero signal to the network's output terminal (designated P). The control network responds to applied select (S) and enable (E) signals so that when the S signal is at a high level (logic 1) and the E signal is at a low level (logic zero) the Q signal is fed to the P output terminal; when the E and S signals are both at a low level, the Q signal is fed to the P output terminal; and when the E signal is at a high level the signal at the P output terminal is held at the low (logic zero) level. This just described enable feature of the invention allows for "wire-OR" connection of the P output terminal from a given ECL circuit to the output terminals of other ECL circuits so as to facilitate the implementation of a variety of processor circuits, such as, for example, toggle/hold circuits, expandable counters, J-K flip-flops and shift registers.
A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the output transimpedance circuits a quantized output signal. A feedback pair of emitter-coupled transistors is interposed between the outputs of the transimpedance circuits and the inputs to the transimpedance circuits. Current pulses are applied alternatively to the common emitter circuits of the input pair and the feedback pair of transistors for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.
A multi-bit latch transceiver is designed to meet the IEEE 1194.1 standard for backplane transceiver logic as specified in the IEEE 896.2 Futurebus+ specification. The latch transceiver features support for live insertion, low skew, controlled rise/fall time (2ns-5ns) and glitch free power-up/down protection. The transceiver utilizes on-chip latches and a built-in bandgap reference that provides very accurate thresholds. Unique slave stage logic in the transceiver's driver stage provides preset input conditions to the slave latch such that data is instantly clocked to the driver output when the driver is enabled, thus reducing propagation delay.
A shift register is disclosed in which an n-stage shift-register chain (sr) consists of 2n series-connected, like basic cells (zi) which are driven in antiphase by a first and a second shift clock (C1, C2) from a clock generator (g). The nonoverlap range of the two shift clocks is temperature- and frequency-stable, so that the shift register can be used within a wide frequency and temperature range. Frequency adaptation is accomplished simply by changing resistance values.
An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit. When operating as a shift register circuit, shift-in data is coupled to the second latch element, and this second latch element operates as the "master" and the third latch element operates as the "slave" of a master/slave latch through which data is selectively shifted by appropriate clock signals.
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a "1", and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.
