A static induction transistor (SIT) which is made to operate with a forward gate bias by maintaining the width of the channel region at an appropriate value. Such an improved SIT is used as the inverter transistor in a merged transistor logic (MTL) semiconductor IC (integrated circuit) to reduce the time delay-power product by an order or more. The collector region of a bipolar load transistor is continuous to or also serves as the gate region of the inverter SIT. A plurality of channel regions are formed penetrating through this collection/gate region. This SIT is simple in structure, which enables a marked increase in the integration density.

An electronic timepiece including a time-base signal source having a quartz vibrator operating at a frequency of 1 MHz or higher, and a multi-stage divider. At least one stage of the divider is comprised of a static induction transistor logic inverter (SITL inverter), which includes a static induction transistor (SIT) and a bipolar load transistor, operating at a bias voltage of or less than 0.5 volts. The time-base signal source may comprise an oscillator circuit which also includes a static induction transistor.

A junction field effect transistor having a source region, a gate region and a drain region, which are laminated to form a laminated layer, and a channel region formed on one side surface across the laminated layer, and also having a cavity which separates high impurity concentration regions of the source, gate and drain regions is disclosed. A method for manufacturing the above junction field effect transistor is also disclosed which has the steps of laminating semiconductor layers which become a source region, a gate region and a drain region, respectively, removing portions of the semiconductor layers other than portions which become an active region portion, and forming a channel region on one side surface across the laminated layers of the source region, gate region and drain region by the epitaxial growth method, and also forming cavities.

A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source region and each of the drain regions, and gate regions defining the respective channel regions therebetween. The extracting region is merged into the gate regions. The channel regions have such dimensions and an impurity concentration that the channels are closed with depletion layers extending from the gate regions at zero gate voltage. The gate regions constitute a logic input and the drains constitute logic outputs. The zero gate voltage renders the channels non-conductive and the raised voltage renders the channels conductive, thus realizing an inverter circuit useful for wired logics.

A static induction transistor of the type wherein carriers are injected from a source to a drain across a potential barrier induced in a current channel and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate and to a drain bias voltage applied to the drain to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R.sub.c and the true transconductance G.sub.m of the transistor is maintained less than one and the product of the true transconductance and the series resistance R.sub.s of the transistor is maintained greater than or equal to one in the low drain current region in the operative state of the transistor. The series resistance R.sub.s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region. In an upside-down structure, the above-mentioned conditions can be easily attained by selecting respective impurity concentrations and thicknesses of a substrate and an epitaxial layer grown thereon.