An information processor is comprised of a plurality of circuits each of which is controlled by firmware and connected to a common bus and has a contention circuit for the bus. An arithmetic control unit for controlling the execution of the firmware is provided with a timing control circuit. When the arithmetic control unit is going to issue a bus use request or has issued the request of when it is issuing an interrupt inhibit instruction or interrupts its operation, another unit connecting to the common bus seizes the bus and interrupts the arithmetic control unit. In such a case, the timing control circuit causes the execution timing of the arithmetic control unit to be in a wait state and accepts the interrupt.
A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.
A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.
A first copy of Open Firmware is loaded into system memory to supply a debug function and a second copy of the same firmware is then loaded to provide functional code which is to be debugged. The first copy of Open Firmware in system memory is designated as the resident debugging function. Kernel code, within the first copy, sets up an executing environment for the debugger, such as system exception handlers and debug console enablement. Normal Open Firmware configuration variables are retrieved from Non-Volatile Random Access Memory ("NVRAM") by the first copy and transmitted to the loader. The second copy of Open Firmware is loaded into system memory to a location specified by the configuration variables. The second copy firmware image is designated as a normal Open Firmware operation in the system. The second copy initially takes over all system exception handlers except instruction breakpoint exception, program interrupt exception and trace exception. The instruction breakpoint exception is utilized to invoke the first copy, or resident debugger, from the normal Open Firmware (second copy) image during code debugging. The two copy debugging configuration is utilized in conjunction with an online machine language assembler and disassembler.
A three level network microprocessor based nodal architecture for a fiber optic local area network communication system is disclosed in which the processing responsibility for establishing a voice, video or data communication link between an initiating I/O device and a recipient I/O device and for subsequent two way data exchange between the initiating and recipient devices are shared between three levels of digital processing capability in such manner as to demand the least amount of time from the highest, most intelligent processing level common to all devices thereby making more efficient use of its processing capability as an overall supervisory processor. Each I/O device whether it be a digital terminal, computer or telephone set interfaces with a nodal system through a middle level of processor. An initial communication request from any device at the middle level generates an interrupt command to the highest supervisory processing level which responds to the interrupt, resulting in the identification of the desired recipient station by recalling from storage, associated with the highest level processor, routing information required in establishing a communication link with the desired recipient device. That information is provided to the processor at the middle level associated with the initiating device. That processor completes the link if the recipient is local to it. Otherwise the addresse or recipient device identifying codes are communicated from the middle level to a third level processor responsible for effecting the actual routing of the communication.
