A memory stable against variation of an external supply voltage is disclosed. The memory comprises a plurality of memory cells, each of memory cells including an insulated-gate field-effect transistor having a gate coupled to a word line, a source and a drain, one of the source and drain being coupled to a digit line, and an information storage capacitor having a first electrode coupled to the other of the source and drain of the transistor and a second electrode, and means for biasing the second electrode with a stabilized voltage.
A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.
A dynamic semiconductor memory device includes a one-transistor one-capacitor type dynamic memory cell and a voltage dividing circuit having a potential providing terminal for providing an intermediate potential between the potential of the power supply and ground potential. One electrode of the capacitor in the memory cell is connected to the potential providing terminal. The voltage dividing circuit includes a potential switching circuit which changes the intermediate potential synchronously with an internal clock signal for selecting a word line, thus preventing a read error.
The present invention pertains to a dynamic memory. The voltage of the hot spot of the storage capacitor is carried to a value such that all the cells comprise the same logic value, owing to a potential generator. It is thus possible to write and read bit fields on a large-capacity memory at high speed. This device has applications with respect to image memories and for manufacturing tests.
A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.
A method and a circuit of reducing cell plate noise induced by memory access are provided. The circuit includes a sample and hold circuit, a differential amplifier and a current source. The sample and hold circuit maintains a sample voltage identical to the normal level of the reference cell plate voltage. The differential amplifier compares the sample voltage with the reference cell plate voltage during memory access in the DRAM and generates a difference voltage corresponding to the cell plate noise. The current source, which is controlled by the difference voltage, can modify the reference cell plate voltage to reduce the cell plate noise during memory access.
