This is a feedback amplifier incorporating shunt feedback pairs which are emitter coupled for differential input transimpedance configuration whose characteristic includes a low differential input impedance and a high common load impedance that uses low input offset voltages to initiate the amplification and a latch coupled thereto to latch and amplify the amplifier input causing the effective amplifier input to be several orders of magnitude greater than the initial offset voltages. Thus, the amplifier of the invention uses the latch to not only sense the output of the amplifier but also the drive and reinforce the amplifier input through feedback.
A data storage element having input and output ports isolated from a regenerative latch portion so that the data transmission path is not through the latch. The circuit arrangement provided greatly reduces the probability of a metastable occurrence and permits data acquisition at a high rate with minimal error, and thus is suitable for use in high-speed digital shift registers.
An improved sense amplifier circuit for sensing information in the cells of a semiconductor memory device is presented. The sense amplifier circuit as presented includes AC-coupled positive feedback means to provide a reduction in sensing delay time, and thus, faster memory access time.
A high speed, low power parallel analog-to-digital converter (100) with comparator (C.sub.j) having sense amplifiers operating with low power, high speed and a ROM encoder (130) also operating in low power, high speed regime.
