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Description  |
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DESCRIPTION
1. Technical Field
The invention relates to charge coupled imaging devices and, more
particularly, to a CCD device including a CCD imaging array that is
operated in the time delay and integration mode to generate a two
dimensional array of charge packets corresponding to the picture elements
of an incident light image and further including a CCD gating and charge
replicating apparatus that averages the two dimensional charge packets in
parallel by columns and then derives area averages for particular picture
elements of the image by a horizontal integration.
2. Background Art
It is known to those skilled in the electrical arts that a charge coupled
device (CCD) array may be employed to provide an electrical representation
of an incident light image by generating charge packets corresponding to
the light intensity of picture elements (pels) of the image. It is also
known that the light sensitivity of the CCD array may be increased if the
array is operated in a time delay and integration mode.
The imaging capability of a CCD array may be further enhanced by deriving
the second derivative, or Laplacian, for the picture elements of the image
and thereby defining the edge transitions of the image more clearly. In
Digital Picture Processing, by Aziel Rosenfeld and Avinash C. Kak, at
Section 6.4, pages 179-191, it is indicated that the second derivative
(Laplacian) for each picture element of a light image may be approximated
by computing the difference between the light intensity measured at a
picture element and the average light intensity measured in an area
surrounding the picture element.
Prior art CCD imagers have derived the Laplacian for each picture element
of an image by irradiating a CCD array with a focused image to form charge
packets proportional to the focused light intensity at the picture
elements of the image and then irradiating the CCD array with the
unfocused image to form charge packets proportional to the average light
intensity around each picture element. The unfocused charge packets are
then subtracted from the corresponding focused charge packets to derive
the Laplacian for each picture element. Such focus/defocus prior art
imaging apparatus has tended to be fairly expensive and complicated since,
in order to generate the charge data, the apparatus must either split an
image into focused and unfocused components to irradiate separate CCD
arrays or must opto-mechanically switch a focused and unfocused image to
irradiate a single CCD array.
A more efficient means of computing the Laplacian is disclosed in a paper,
"A Multiple Output CCD Imager for Imaging Processing Applications", by J.
E. Hall, J. F. Brietzmann, M. M. Blouke, J. T. Carlo; Int. Electron
Devices Meeting Tech. Digest, Washington, D.C., Dec. 4-6, 1978, pp.
415-418. The disclosed imaging device includes an imaging array and a
peripherally placed serial register that is employed to serially gate line
charge packets from the imaging array. Charge packets at particular points
of successive imaged lines are tapped off at fixed points on the serial
register and are summed to compute area averages for the picture elements
of the image. The apparatus has the disadvantage that transfer
inefficiencies in the serial gating process tend to degrade the electrical
representation of the image in proportion to the number of transfers that
are executed. Accordingly, the serial transfer summing apparatus becomes
less accurate as the number of picture elements in the line of an image
increases. Thus, the accuracy of the apparatus is significantly reduced
for images having a relatively large number of picture elements, for
example, on the order of 2000 pels per line. Also, the length of the
serial register increases in proportion to the number of lines that are
required to compute an area average and, due to transfer inefficiencies,
the increased register length results in decreased accuracy.
In order to reduce the effect of transfer inefficiency in computing the
second derivative, or Laplacian, it is necessary to compute area averages
about individual pels of an image by summing a plurality of columns of
pels in a parallel fashion. However, the parallel summing must not destroy
the individual charge packets of the imaging array, since the individual
charge packets must be available to compute the Laplacian at each pel.
Non-destructive summing has been used in the prior art to compute the
values of the Hadamard matrices for semiconductor imaging arrays. For
example, such systems are disclosed in the U.S. Patent to Engler, U.S.
Pat. No. 4,011,442, "Apparatus for Sensing Optical Signals", issued Mar.
8, 1977; and the U.S. Patent to Michon, U.S. Pat. No. 4,129,887, "Solid
Stage Imaging Apparatus", issued Dec. 12, 1978. However, such prior art
apparatus has not been employed to compute area averages and to derive the
second derivative (Laplacian) for the pels of an imaging array. In
addition, prior art algebraic summing apparatus has tended to be somewhat
complicated in structure and operation.
A relatively simple semiconductor apparatus for non-destructively
replicating charge packets is disclosed in the U.S. Patents to Heller,
U.S. Pat. Nos. 4,047,151, "Method and Apparatus for Replicating a Charge
Packet", issued Sept. 6, 1977, and 4,035,667, "Input Circuit for Inserting
Charge Packets into a Charge-Transfer Device", issued July 12, 1977.
However, the disclosed charge replication devices have not been employed
to generate area averages and to compute a second derivative for the
picture elements of an image.
Accordingly, it is an object of the invention to provide a relatively
simple and compact charge coupled device having means for quickly and
accurately deriving a charge representation of a second derivative
(Laplacian) for the picture elements of an irradiating image. A further
object of the invention is to provide such a CCD device wherein area
averages for particular picture elements are computed in parallel to
reduce the effect of transfer inefficiency on the computation of the
Laplacian.
Another object of the invention is to provide a CCD device wherein a
relatively large picture element averaging area, for example 5
pels.times.5 pels, may be employed to derive a Laplacian without unduly
reducing the accuracy of the computation.
A further object of the invention is to provide a Laplacian-generating CCD
device that may be operated in conjunction with a CCD imager that is
operated in a time delay and integration mode.
A further object of the invention is to provide such a Laplacian-generating
CCD device with a structure that is sufficiently compact to fit on a
single chip and that may operate with images having line widths greater
than 2000 pels.
These and other objects of this invention will become apparent from a
review of the detailed specification which follows and a consideration of
the accompanying drawings.
DISCLOSURE OF THE INVENTION
In order to achieve the objects of the invention and to overcome the
problems of the prior art the improved charge coupled device, according to
the invention, includes a time delay and integration CCD imaging array
that generates successive rows of charge packets corresponding to the
light intensity of associated rows of picture elements of an incident
light image.
A line image storage array is disposed to receive successive rows of charge
packets from the TDI array and to store five rows of charge packets at one
time, the rows being arranged in separate vertical summing columns.
A replicator summing means is provided to generate a replicated sum charge
for each column of the line image storage array, each replicated sum
charge is proportional to the sum of the charges stored in an associated
column of the array. The third charge in the column associated with each
replicated sum charge is designated the "middle charge" of the charge sum.
Parallel gating delay electrodes are employed to synchronize the gating of
a row of replicated sum charges into an area average serial shift register
with the gating of a row of associated middle charge packets into a
focused element serial shift register.
The serial shift registers are then synchronously gated in a serial fashion
and, as the registers are gated, the five endmost replicated sum charges
are summed by a horizontal summing means and 1/25 of the charge sum thus
derived is subtracted by a comparing means from an associated central
charge that is stored in the focused element serial shift register. The
difference charge at the output of the comparing means is proportional to
the second derivative (Laplacian) of the stored central charge.
A preferred embodiment of the charge coupled device of the invention is
implemented in a structure utilizing four phase clock gating and having
two levels of polysilicon electrodes and a top level of aluminum
cross-over electrodes.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a diagrammatic representation of a two dimensional array
of charge packets corresponding to the picture elements of a portion of a
light image.
FIGS. 2, 2A and 2B illustrate a block diagram of a CCD imaging device and
Laplacian-generator in accordance with the invention.
FIG. 3 illustrates a top elevation view of a portion of a CCD device in
accordance with the invention.
FIGS. 4A and 4B illustrate a cross-sectional side elevation view of the CCD
apparatus of FIG. 2, taken along a line A--A in the direction of the
arrows.
FIG. 5 illustrates a diagrammatic view of the electrodes and associated
energy wells that are generated by the CCD device of FIG. 2 in creating a
charge sum replica that is proportional to the sum of a column of stored
charges.
FIG. 6 illustrates a timing diagram of the operational signals for the CCD
device of FIG. 2.
BEST MODE FOR CARRYING OUT THE INVENTION
The remaining portion of this specification will describe preferred
embodiments of the invention when read in conjunction with the attached
drawings, in which like reference characters identify identical apparatus.
FIG. 1 illustrates a grid of charge packets such as is generated by an
imaging device, for example a CCD, in response to an incident light image.
The magnitude of each charge packet of the grid corresponds to the
intensity of light measured by the CCD for a particular corresponding
picture element of the incident image. Thus, charge packets 1P1-1P7
correspond to the light intensity registered at one column of picture
elements of the incident image. Of course, successive columns of charge
packets correspond to additional columns of picture elements of the image.
It is known in the art that the effectiveness of the image processing of
such charge data may be enhanced and, in particular, the edges of a
processed image may be more clearly defined, if the Laplacian is derived
for at least some of the charge packets of the array of FIG. 1. The
Laplacian for each element or pel of the array provides an indication of
whether the particular element or pel represents a dark or a light tone
for a processed image.
The Laplacian for each pel is calculated by measuring the average
brightness within an area surrounding the pel, and subtracting the average
brightness from the brightness measured at the pel. It has been determined
that a 5.times.5 area of pels is satisfactory for many applications for
obtaining an average brightness measurement. Thus, for example, if it is
determined to measure the average brightness about the charge packet 3P3
of FIG. 1, it is necessary to sum the charges measured within an area five
pels on a side and having the charge 3P3 at its center. More particularly,
the average brightness about the pel 3P3 may be derived by computing an
area sum:
##EQU1##
where j designates the column position and k designates the row position
of a charge packet. The Laplacian for 3P3 may then be approximated by
subtracting a charge proportional to 1/25 of the area sum from the charge
3P3.
Thus, it should be understood that the Laplacian for the charge packets of
FIG. 1 is computed by deriving a plurality of area averages for
overlapping 5.times.5 pel areas. In general, the area sum for a charge
packet .sub.C P.sub.R is defined by:
##EQU2##
FIG. 2 illustrates a block diagram of a charge coupled apparatus, in
accordance with the invention, that is employed to compute two dimensional
area averages for the charge packets formed by a CCD imaging device 1 and
to derive the Laplacian for each charge packet. The imaging device 1 of
the preferred embodiment of FIG. 1 is operated in a time delay and
integration mode to enhance the sensitivity of the array to incident
light.
As is known to those skilled in the CCD imaging art, such a TDI array
includes a plurality of horizontally oriented parallel shift registers 3
that each define a horizontal row of resolution elements or cells 5 that
operate to convert incident light energy to a corresponding electric
charge. The quantity of electric charge that is generated at a cell is,
within known saturation limits, proportional to the intensity of the
incident light and the time during which the incident light irradiates the
cell of the CCD.
In operation, an incident light image is scanned downward across the rows
of cells of the parallel registers 3 and the parallel registers are
synchronously gated so that a plurality of charge packets corresponding to
the picture elements of the image accumulate under the image as the image
moves over the parallel registers. Thus, after a particular line of the
image has moved over all of the parallel registers of the CCD array, a
lower end row of cells of the array contains the final accumulated charge
packets that correspond to the light intensity of the line. As charges are
gated in parallel from the end row, new charges from the preceding row are
gated into the end row.
In accordance with the invention, charge packets of the end row of the CCD
array 1 are gated in parallel to associated cells 1Q1, 2Q1, 3Q1, 4Q1, 5Q1
. . . and nQ1 of a first row of a line image storage array 7. As each row
of accumulated charge packets from the end row of the CCD array 1 is
received by the first row of the line image storage array, preceding rows
of the line image storage array are synchronously gated downwardly to make
room for the added row of charge packets.
As the parallel gating through the line image storage array proceeds, the
last row of charge packets at cells 1Q5, 2Q5, 3Q5, 4Q5, 5Q5 . . . and nQ5
are gated in parallel to associated cells S1Q3, S2Q3, S3Q3, S4Q3, S5Q3 . .
. and SnQ3 of a focused picture element serial shift register 9. Thus,
each cell of the serial shift register 9 contains a charge packet
corresponding to the measured light intensity of a particular picture
element of a line portion of an image that is scanned across the CCD array
1.
In accordance with the invention, a replicator summation circuit 11 is
provided to non-destructively form replicated charge packets that are each
proportional to the sum of the charges stored at a particular column 13 of
the line image storage array 7 at a particular instant in time. Thus, the
replicator summer will generate at position 18 a charge packet having a
charge magnitude that is proportional to the sum of the charge packets
stored at cells 1Q1, 1Q2, 1Q3, 1Q4 and 1Q5 of the associated 1Q column of
the line image storage array 7. Successive positions of the replicator
summer will have replicated charge packets corresponding to the sum of the
charges stored at associated successive columns of the line image storage
array.
Each row of replicated charge packets is gated in parallel to an area
average serial shift register 17 through a gating delay device 15. The
gating delay device 15 operates to gate a row of replicated charge packets
into the serial shift register 17 at the same time that a corresponding
row of middle charge packets is gated into the serial shift register 9.
The middle charge packet for each replicated charge is the charge packet
that was stored at a corresponding middle column position (1Q3, 2Q3, 3Q3,
4Q3, 5Q3 . . . nQ3) of the image storage array 7 when the replicated
charge packet was formed. Thus, for example, the replicated sum of the
charges stored at the 1Q column of the image storage array at a particular
instant in time is gated into a cell 19 of the register 17 when the charge
at the middle position 1Q3 of the column at the particular instant in time
is gated into the position S1Q3 of the serial shift register 9.
Accordingly, immediately after a parallel shift of charge packets into the
registers 9 and 17, the register 17 will contain column sum charges and
the register 9 will contain corresponding middle charges.
After a row of middle charges is gated in parallel into the shift register
9 and associated replicated column sum charge packets are gated in
parallel into the shift register 17, the stored charge packets in the
registers 9 and 17 are serially and synchronously gated to the right. When
a middle charge packet of the register 9 is gated into a cell 21 of the
register 9, the charge packet is applied to an input 22 of a comparator 23
that may be constructed and operated, for example, as shown in the IBM
Technical Disclosure Bulletin, "Magnitude Differencing Circuit", by D. L.
Critchlow et al, Vol. 18, No. 9, pg. 3071 (February 1976) or as disclosed
in the U.S. patent application of James White, Non-Destructive Charge
Transfer Device Differencing Circuit, Ser. No. 19,211, filed Mar. 9, 1979.
The disclosures of the Technical Disclosure Bulletin and of the
application are incorporated herein by reference.
A charge having a magnitude corresponding to the area average about the
middle charge applied at the input 22 is applied to the other input 24 of
the comparator 23 and the comparator generates a signal, for example a
charge or a voltage, that is proportional to the difference between the
two applied charges. The output signal of the comparator 23 is an
approximation of the second derivative, or Laplacian, for the middle
charge that is applied at the input 22. Of course, as the registers 9 and
17 are gated serially to the right, successive middle charges and
associated area sum charges are applied to the comparator and
corresponding Laplacian output values are generated. The Laplacian output
values are applied to improve edge detection in a manner known to the art.
The area average charge for the middle charge packet stored at 21 is
generated by dividing the sum of the replicated column sum charge packets
of the last five cells of the serial shift registers 17 by 25. The
division of the five replicated column sum charge packets may be performed
by any manner known to the art. For example, as shown in FIG. 2, each of
the replicated charge packets of the last five cells of the register 17 is
initially divided by five by applying the charge packet to a split
electrode charge divider 26 having five equal area electrodes. One
electrode of each cell of the last five cells is then extended to
conductively connect to a common bus 25 and the common bus 25 is shaped to
form five additional split electrode charge dividers 28. A single
electrode of the additional electrodes is extended to conductively connect
to the input 24 of the comparator 23. Thus, 1/25 of the total charge
stored at the last five cells is applied to the comparator 23.
As explained previously, the embodiment of FIG. 2 is employed to generate
an area average for each image picture element, the area average being
determined over a square area five pels on a side and centered about a
particular focused pel. Thus, it will be appreciated that the line image
storage array 7 of FIG. 2 is comprised of five storage rows that define
the five pel vertical measurement of the averaging area. It should be
understood that if a larger or smaller averaging area is desired, the
number of storage rows of the line image storage array 7 may be adjusted
accordingly. For example, if a 3.times.3 averaging area for each pel is
desired, only 3 storage rows need be employed for the line image storage
array of FIG. 2.
It should be further understood that each horizontal row of the line image
storage array 7 may include any desired number of storage cells. Thus,
although FIG. 2 illustrates only 10 cells in each horizontal row, any
number of cells may be employed. For example, a typical device may have
storage rows extending to include more than 2000 pels.
The horizontal dimension of the averaging area is determined by the number
of cells that are included in computing the horizontal charge sum at the
end of the serial register 17. In the preferred embodiment of the
invention, the last five cells are employed to derive a horizontal sum.
However, a larger or smaller number of cells may be used if a
corresponding larger or smaller averaging area is desired.
If the vertical or horizontal extent of the averaging area is changed, the
number of split electrode charge dividers must be altered accordingly.
Thus, if an averaging area having a vertical dimension of m pels and a
horizontal dimension of n pels is desired, m divider electrodes 26 are
required for each of the last n cells of the register 17 and n divider
electrodes 28 are required for the common bus 25.
FIG. 3 illustrates a top elevation view of a charge coupled device that may
be employed to generate an approximation of the second derivative for each
of the picture elements of an imaging array. FIG. 4 illustrates a
cross-sectional view of a portion of the CCD device of FIG. 3, taken along
the line A--A in the direction of the arrows. As shown in FIG. 4, the CCD
device of FIG. 3 is supported by a P-type substrate 30 that may be made,
for example of silicon.
The device of FIG. 3 includes a CCD imaging array that may be operated in
the time delay and integration mode to generate successive rows of charge
packets corresponding to the intensity of the incident light at an
associated row of cells or picture elements of the array. Such CCD/TDI
imaging arrays are well known to the art and, therefore, the imaging
portion at the top of the device of FIG. 2 is not completely illustrated.
It should be understood that although the device of FIG. 3 uses a CCD
imaging array operated in the TDI mode, other known imaging devices may
also be employed without departing from the spirit of the invention. For
example, linear CCD arrays or photodiode arrays may also be employed to
generate charge packets in response to an incident light image. Also,
bucket brigade devices (BBDs) may be employed to generate charge packets
in the TDI mode.
The last four parallel electrodes of the imaging array are shown to
illustrate the means whereby a row of charge packets from the imaging
array is applied to the Laplacian-generating apparatus of the invention.
As shown in FIG. 3, the end portion 32 of the imaging array includes
amorphous polysilicon parallel electrodes that are arranged in insulated,
overlapping relation with respect to one another to gate a row of charge
packets downwardly in response to serially applied .phi..sub.1V,
.phi..sub.2V, .phi..sub.3V and .phi..sub.4V clock signals. The charge
packets are moved along associated charge transfer channels 27 that are
defined by strips of channel stop regions 29 that may be comprised, for
example, of silicon dioxide and that are overlapped by the parallel
polysilicon electrodes.
The parallel electrodes of the imaging array are embedded in insulating
material, for example silicon dioxide, that supports and separates the
electrodes at either a poly 1 level with respect to the substrate 30 or a
poly 2 level. The topmost illustrated parallel electrode 34 is supported
in the silicon dioxide at the poly 2 level and an adjacent overlapping
parallel electrode 36 is supported in overlapping relation with the
electrode 34 at the lower poly 1 level. The electrode 36 is supported
above the surface of the substrate 30 by a layer of silicon dioxide and is
separated from its associated overlapping electrode 34 by another layer of
silicon dioxide.
The parallel electrode 34 is operated to form a row of potential wells to
receive charge packets in response to an applied .phi..sub.4V clock
signal. The adjacent electrode 36 forms adjacent energy wells to receive
the charge packets in response to an applied .phi..sub.1V clock signal. A
third illustrated parallel electrode 38 is positioned at the poly 2 level
in overlapping relation to the parallel electrode 36 and is operated to
form potential wells to receive charge packets in response to an applied
.phi..sub.2V clock signal. The next successive electrode 40 is positioned
at the poly 1 level and operates to form a row of potential wells in
response to an applied .phi..sub.3V clock signal. The last parallel
electrode 31 of the imaging array is positioned at level poly 2 and is
operated to form potential wells and receive charge packets in response to
a 100.sub.4V clock signal.
The charge packets on the last parallel electrode 31 of the imaging array
are received by a first parallel electrode 48 of the line image storage
array 7 in response to the .phi..sub.1V clock signal. The parallel
electrode 48 is positioned at level poly 1 and is arranged in overlapping
relation with a second parallel electrode 50 that receives a row of charge
packets in response to an applied .phi..sub.2V clock signal. An
overlapping parallel electrode 52 is positioned at level poly 1 to receive
charge packets from the parallel electrode 50 in response to an applied
.phi..sub.3V clock signal. The electrode 52 is arranged in insulated
overlapping relation to a first row of adjacent, separate column
electrodes 35 that are each positioned at level poly 2 and that may be
comprised, for example, of poly-silicon. Each of the column electrodes is
positioned to receive a single charge packet from an adjacent portion of
the overlapping input electrode 52. The column electrodes 35 are arranged
in five rows, corresponding to the intended five row vertical dimension of
the averaging area. It should be appreciated that the number of rows of
column electrodes 35 will vary in accordance with the intended vertical
dimension of the averaging area. For example, if it is desired to provide
an averaging area having a three pel vertical dimension, there will only
be three rows of column electrodes 35 provided for the device of FIG. 2.
However, the preferred embodiment of FIG. 2 utilizes five rows of column
electrodes 35 since it has been determined that an averaging area having a
vertical dimension of five pels and a horizontal dimension of five pels is
sufficiently large to provide an accurate approximation of the Laplacian
for single pels for many useful applications.
For the sake of simplicity, only seven column electrodes are shown for each
row of the line image storage array. However, it should be understood that
the rows may include any number of column electrodes. In a preferred
embodiment of the invention, in excess of 2000 column electrodes are used
for each row.
The rows of column electrodes are separated by intermediate poly-silicon
parallel gating electrodes that are responsive to the .phi..sub.1V,
.phi..sub.2V and .phi..sub.3V clock signals to move rows of charges
between the rows of column electrodes. The intermediate parallel gating
electrodes are arranged in insulated, overlapping relation as explained
above.
Each column of column electrodes 35 is covered by a vertical cross-over
electrode 37 made, for example, of aluminum. Each vertical cross-over
electrode 37 is separated from its associated column of column electrodes
by an insulating layer, for example of silicon dioxide. However, each
column electrode 35 of a column is conductively connected to its
associated cross-over electrode 37 by means of contact holes 39 that allow
the conducting material of the cross-over electrodes to extend down to the
poly 2 level to contact the associated column electrodes.
Thus, if a voltage signal is applied to a vertical cross-over electrode 37,
the signal will also be applied to the associated column of column
electrodes 35. Accordingly, potential wells may be created at each column
electrode 35 of a particular column by applying a clock signal to the
associated vertical cross-over electrode 37. It should be understood that
if a potential well is created at a column electrode 35 in the
above-described manner, the column electrode may receive a charge packet
that is positioned under an adjacent overlapping parallel electrode. For
example, each of the column electrodes 35 of the first row may receive
charges stored at the associated overlapping parallel electrode 52 if a
gating signal is applied to the associated vertical cross-over electrodes
37 and is removed from the electrode 52.
A charge packet may be removed from beneath a column electrode 35 if a
.phi..sub.1V gating signal is applied to an adjacent, overlapping
electrode. For example, a parallel electrode 54 may receive charge packets
stored at the first row of column electrodes 35 in response to an applied
.phi..sub.1V clock signal followed by the removal of the gating signal
from the electrodes 37. Thereafter, the charges from a row of column
electrodes 35 may be moved to the next successive row of column electrodes
by serially applying the .phi..sub.2V and .phi..sub.3V gating signals to
activate associated intermediate parallel electrodes and timely removing
gating signals .phi..sub.1V and .phi..sub.2V to deactivate respective
electrodes as charge is removed.
The vertical cross-over electrodes 37 pass over the serial shift register 9
and are separated from the apparatus of the serial shift register 9 by an
insulating layer, for example of silicon dioxide. The serial shift
register 9 is employed to receive successive rows of charge packets in
parallel from the last row of column electrodes 35 and to thereafter gate
each row of the received charge packets in a serial fashion.
The serial shift register 9 is comprised of four parallel, horizontally
extending electrodes having vertically extending tabs arranged to form
overlapping serial electrode portions that may be energized by
sequentially applied serial clock signals .phi..sub.1 H, .phi..sub.2H,
.phi..sub.3H and .phi..sub.4H to create associated serial potential wells.
The serial wells are employed to store the received charge packets and to
move the charge packets in a serial direction. A top electrode 41 of the
shift register 9 is positioned at level poly 1 and is employed to receive
the charge packets from the last row of column electrodes 35 of the line
image storage array 7 in response to a .phi..sub.1H clock signal. A second
electrode 42 is arranged at poly 2 in insulated overlapping relation to
the top serial electrode 41 and is disposed to receive charge packets from
the top serial electrode in response to a .phi..sub.2H clock signal. A
third electrode 44 is disposed at level poly 1 and is arranged in
insulated overlapping relation at its tab extensions to the second
electrode 42 in order to receive the charge packets on the second serial
electrode in response to an applied .phi..sub.3H clock signal. Likewise, a
fourth electrode 46 is disposed at poly 2 in insulated overlapping
relation to the third electrode 44 and is operated to receive the charge
packets of the third electrode in response to an applied .phi..sub.4H
clock signal. Sequential applications of the .phi..sub.1H, .phi..sub.2H,
.phi..sub.3H and .phi..sub.4H gating signals cause stored charges in the
serial shift register 9 to move in a serial direction to the right along a
serial charge transfer path.
The vertical cross-over electrodes 37 also extend to cover a conductive
source diffusion region 43 that is formed in the silicon substrate 30 and
a poly-silicon gate electrode 45 that is positioned in insulated relation
at level poly 1. Each vertical cross-over electrode 37 includes a contact
hole 47 that extends to an underlying diffusion region 49 that is formed
in the substrate 30 of the device. Each vertical cross-over electrode 37
is conductively connected to its associated underlying diffusion region 49
through its contact hole 47.
A poly-silicon reference electrode 51 is positioned at level poly 2 and is
responsive to a threshold voltage signal V.sub.TX to form a reference
barrier at a particular threshold level with respect to the diffusion
regions 49. It should be understood that the source diffusion region 43,
associated first gate electrode 45, and diffusion regions 49 form a line
of IGFETs that may be operated by a gate signal V.sub.RD1 on the first
gate electrode 45 to apply a particular operational voltage V.sub.DIFF1 on
the source diffusion region 43 to the vertical cross-over electrodes 37.
A poly-silicon replica storage electrode 55 is disposed at level poly 1 and
includes vertically extending tab portions that overlap the reference
electrode 51 and are separated from the reference electrode 51 by an
intermediate layer of silicon dioxide. The replica storage electrode 55
forms potential wells at its upwardly extending vertical tab portions in
response to a .phi..sub.1A clock signal and thereby receives charge
packets that pass from associated adjacent portions of the diffusion
regions 49 and move past the potential reference barrier created at the
reference electrode 51.
A second poly-silicon gate electrode 53 is positioned at level poly 2 in
insulated overlapping relation with the vertical extending portions of the
replica storage electrode 55. The second gate electrode 53 is separated
from the replica storage electrode 55 by an insulating layer of silicon
dioxide. A diffusion cross-over electrode 57 made, for example of
aluminum, is disposed to overlap the second gate electrode 53 and is
separated from the second gate electrode by an insulating layer of silicon
dioxide. The diffusion cross-over electrode 57 has a plurality of contact
holes 59, and each hole extends to an n+ drain diffusion region 61 that is
disposed in the substrate of the device. The diffusion cross-over
electrode 57 conductively contacts the drain diffusion regions 61 through
the holes 59.
A charge may be drained from the potential wells formed at the replica
storage electrode 55 by applying a gate voltage V.sub.RD2 to the second
gate electrode 53 to form a lower potential well at the gate electrode 53
and by applying a positive diffusion voltage V.sub.DIFF2 to the diffusion
cross-over electrode 57 to create drain wells that will receive the
charges stored at the replica storage electrode 55.
It should be understood that the structure and | | |
