An efficient method for purging cache memory sub-blocks within a cache memory block is disclosed. The method is particularly applicable to cache memories established on rotating magnetic media, such as a hard disk drive. The method is unique in that it requires absolutely no system overhead when the system is running and the cache is not completely full. When all sub-blocks within the cache memory have been filled, sophisticated, system resource-intensive algorithms are not employed to determine which is the oldest or the least frequently used sub-block of data. Instead, sub-blocks of data are removed in a pseudo-random manner until ample space is available within the cache.

A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entries are simultaneously compared with one or more dynamic lookaside address translator (DLAT) translated absolute addresses. Compare signals, one for each class entry per DLAT absolute address, are routed to a synonym detection circuit. The detection circuit simultaneously interprets all directory compare signals and determines if a principle hit, synonym hit or a miss occurred in the cache for each request. A principle hit occurs in the group selected by the translatable part of the requested address, and a synonym hit occurs in one of the other groups. If a synonym hit is detected, the group identifier bits for the group having the hit are concatenated with the non-translatable bits used as the cache address for locating the required cache data. For a set-associative cache, set identifier bits are simultaneously generated for cache addressing.

A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

A data processing system includes virtual-addressed and real-addressed stores. Whenever an addressed location is not resident in the memory in which it is attempted to be accessed, the address is translated to the other address space. If a virtual address cannot access the desired location in the virtual memory the virtual address through a virtual-to-real translator is translated to a real address and the location is addressed in the real memory. Whenever a real address needs to access a virtual address in the virtual-addressed memory, the real address is converted through a real-to-virtual translator in order to locate corresponding locations in the virtual-addressed memory. Virtual-to-real translation is carried out by storing the real addresses corresponding to a virtual address in a translation lookaside buffer. Entry to the translation lookaside buffer is gained by using a TLB pointer in a tag array which points to the TLB address which contains the desired real address. By storing a TLB pointer in the tag array rather than storing the full address, many bits are saved in the tag array.

A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.