A differential amplifier is provided which has a low systematic offset voltage and a small variation in quiescent current with respect to variations in processing and temperature while providing low input referred noise and good output drive capability. Each transistor of a differential input pair of transistors is coupled to a plurality of series-connected transistors which are fabricated with substantially equal control electrode dimensions to form composite load tranistors. An output stage having conventional source and sink transistors is coupled to the differential pair of transistors. The sink transistor is implemented as a composite transistor by a plurality of parallel-connected transistors, each also having substantially the same control electrode dimension. Since all the ratioed transistors have equal control electrode dimensions, variations over processing and temperature are minimized. The composite load transistors have a large effective gate length for low input referred noise, and the composite transistor of the output stage has a small effective gate length to provide good drive capability.

An integrated circuit operates as a current-mirror type CMOS amplifier. The integrated circuit is constructed of a first inverter and a second inverter. The first inverter is formed of a first P-channel FET whose source is connected to a power supply with a gate and a drain thereof being connected to a first node; and a first N-channel FET whose drain is connected to the first node with a gate thereof being connected to a first input terminal and with a source thereof being earthed. The second inverter is formed of a second P-channel FET whose source is connected to a power supply with a gate thereof being connected to the first node and with a drain thereof being connected to a second node; and a second N-channel FET whose drain is connected to the second node with a gate thereof being connected to a second input terminal and with a source thereof being earthed. The first inverter and the second inverter having different conductances which vary according to a predetermined ratio in order to reduce current consumption.

The comparator circuit of the invention is provided with a bias voltage generating section which produces a bias voltage corresponded to an output voltage of a differential amplifier section. The bias voltage of the bias voltage generating section is applied to the load elements of a linear amplifier section, which have the same characteristic respectively. On the other hand the output voltage from the differential amplifier section is converted into DC operating point voltage of the linear amplifier section, which is applied to the drive elements of which characteristics are same each other.

A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

A differential amplifier with common-mode rejection for low supply voltages has a first and a second differential pair without transistors in the tails of the differential pairs and with proportional common-mode currents flowing through the first and the second differential pair. The differential amplifier includes a current mirror which feeds the common-mode current of the second differential pair (3, 4) back to the output terminals of the first differential pair for the rejection of common-mode currents at the output terminals. The voltage at the output terminals of the current mirror has a d.c. level which can be established by means of a first reference voltage source independently of the common-mode voltage at the input terminals of the differential amplifier.