A modem fault detector and corrector system including: a first modem including a first transmitter and first receiver and a second modem including a second transmitter and second receiver; switch means for selectively switching the first and second transmitters on and off of a transmission line; and the first and second receivers on and off of a receiver line; and for connecting one of the receivers with the output of either of the first and second transmitters; means for monitoring the status of each of the modems; means for correlating transmit data with receive data; means for sequencing the switch means to enable the means for correlating to compare transmit data selectively with the output of the first transmitter and the second transmitter; and means, responsive to the means for monitoring, the means for correlating, and the means for sequencing for detecting a malfunction in one of the first modem, second modem and transmission-receiver lines and directing the switch means to replace a malfunctioning on-line modem with the off-line modem.

The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels for data and control signals exist between each module and its (N, S, E and W) neighbors and a target module in the array may be addressed by setting up a path through the array from an entry module to the target module. The addressing is effected by sending a stream of link commands, each of which tells a module to link on to its (N, S, E or W) neighbor. Each module responds to the first command of the stream and then sends on the stream stripped of this first command. In an alternative embodiment the link commands are transmitted from module to module in parallel, each module responds to the command at the least significant end and strips it off by a shift of the commands in the least significant direction before the commands pass to the next module. A control circuit for addressing modules in the array at random forms a unique set of link commands for each module to be addressed, these command sets being such that the paths to the various modules form a densely branching tree commencing from the entry module.

A loop transmission system including a plurality of stations connected in series in a looped transmission line to transfer data among the stations, wherein the stations include a supervising station and at least one terminal station and the transmission line is duplicated so that when a fault occurs in currently used one of the transmission lines, the other transmission line which has been used as a spare is used for transmission of data, while the supervising station sends out a specific signal to the spare transmission line and the terminal stations each determines one of the transmission lines through which the specific signal is detected, as the spare.

A communication network comprised of a first, second and third controller node. Each of the controller nodes includes a microprocessor for generating and receiving data messages. The first nodes has a transmit pin in line communication with the receive pin of the second nodes and has a receive pin in line communication with the transmit pin of the second node. The third controller receive pin is in line communication with the transmit pin of the first node and its transmit pin is in line communication with the receive pin of the first node. The microprocessors are programmed to respond to and generate suitable formatted data message bytes. The microprocessors are further programmable to respond only to a unique address-command data message byte from the message source node. The microprocessor will then issue a reply message byte to the destination node. The transmitting node will then send a data message. Where the receiving node is the third node, a data message from the third node must then follow. The protocol is software implemented and includes means of detecting a message error and resolving transmission line content.

An adapter No (n-1) propagates a daisy-chained grant signal directly to the adapter No (n) and a by-passed grant signal to the adapter No (n+1) case. The adapter No (n) is responsive to the status of the previous adapter in the chain, for determining which of the regular grant signal ("GR") or by-passed grant signal ("GRA") has to be taken account of by the succeeding adapter, when the latter wants to access the transmission bus (11). Further, the adapters connected to the chain may be partitioned into groups (80) within which the grant signal is distributed in parallel to the adapters, and propagated to the next group only when none of its adapters (10) requests access to the transmission bus. The same priority level is given to each adapter or group of adapters connected to the daisy-chain, and permits said chain to remain operative even when several adapters are unplugged or malfunction.