An alpha-numeric character generator arrangement having a character store (ROM) in which characters are stored in a character format contained within a co-ordinate character matrix of 10.times.6 discrete character elements. For television interlaced display using a 625-line standard, whole character shapes are displayed in both odd and even fields. For television interlaced display using a 525-line standard, only partial character shapes are displayed in each field, by omitting certain character element rows which are different for each field. The stored character set is so chosen in relation to the omitted character element rows that flicker is minimized. The reduced sized characters, as displayed, allow the same number of rows of characters per frame for the 525-line standard as for the 625-line standard.

In an information output device, character data is read from a font memory and temporarily stored in a data buffer circuit and then dot-expanded to a full-dot memory. A data character is read from the font memory in units of a word and is written into a stage of the data buffer circuit while being laterally shifted so as to selectively position the character. The character is expanded or reduced by duplicating or eliminating the write operation for selected words at the time of reading the data from the data buffer circuit into the full-dot memory. Thus, the data buffer circuit operates to perform both the functions of character positioning and character expansion/compression.

A data display apparatus employs a raster scan cathode ray tube (1), a character refresh buffer (2) and three character row buffers (5,6,15) to address a character generator (3) in conjunction with a slice counter (4) or offset slice counter (18) under control of an events control module (20). This enables data within a partition on the CRT to be scrolled smoothly (scan-line-by-scan-line) and characters of different height (requiring different numbers of scans) to be displayed on the same row of the CRT.

In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.

A microprocessor based CRT video display system includes a microprocessor, a memory and a video processor and controller. The video processor and controller incorporates data and address bus structure in which a plurality of programmable registers are connected to both the data bus and the address bus. The programmable registers arranged along the data and address buses permit efficient retrieval of information from memory for display and also permit the video display system to provide a number of advantageous system features.