A video display terminal is disclosed for use in displaying images of data characters on a display screen. Multi-bit coded data words are supplied by a data source, such as a memory, to a character generator circuit which controls the display of data characters on the face of a video display screen. The coded data words generally fall into three categories; to wit, character codes, control codes and attribute codes. Character codes describe the type of character to be presented on the screen. Attribute codes present modifications or special conditions to be used in conjunction with a displayed character. Control codes are used in conjunction with the control circuitry employed by the character generator. A programmable logic array is interposed between the data source and the character generator and the logic array is programmed so as to interpret the various coded words in various ways to provide output coded words having bit patterns which may be the same or different from that which was inputted from the data source. Consequently, the meaning of an inputted data word may be changed, so that for example, a data word representative of a particular control code may be interpreted to mean a particular character, thereby increasing the available codes to describe characters.
A logic system is provided in a video system for accommodating the display of video data characters and the application of visual attributes to such characters whether occurring singularly or in fields.
The present invention describes an integrated text and data processing system allowing processing of link data before output. The system also provides simultaneous dual emulation of a display and printer normally associated with a host data processor. In accordance with the first aspect of the invention, an input/output terminal includes a support logic circuit for interconnecting the input/output terminal to a port of an intermediate control unit attached to a central processing unit. The input/output terminal includes separate link and display buffers whereas link data may be stored in the link buffer for processing before output to the display associated with a text processor. In accordance with another aspect of the invention, the input/output terminal may include a plurality of support logic circuits each connected to one of the ports of one or more control units associated with one or more central processing units. This structure allows the text processor in the input/output terminal to simultaneously yet independently emulate a display and printer normally associated with a host central processing unit.
The invention selectively designates a specific portion of information which is stored in a memory to identify information which is to be corrected. It further enables a correction of only the suitably designated portion. The read out of information having the corrected information is set in a state which is ready for use. Accordingly, it is not necessary to use a bit addressing circuit, as used in the prior art, this simplifying both the circuit design and the wiring. It is also possible to designate more than one arbitrary item of information as portions which are to be corrected and then to correct all designated information simultaneously. Thus, the read out information is corrected at a high speed. In addition, the number of information items which are capable of correction is not limited by unnecessary bit addressing. This enables an increase in the number of memory elements, and makes the system quite useful as a control device for CRT display systems.
A display terminal control system applied to an image information terminal is disclosed, which includes a system control circuit, a display control circuit having a display buffer memory, the operation thereof being managed by the system control circuit, a coupler connected to the system control circuit for coupling the image information terminal to a data center and a keyborard connected to the system control circuit, wherein the keyboard has a multi-image control key which enables a multi-image display for normal image data sequentially supplied from the data center.
In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible. The PLA also contains self-test microcode which permits the console operator to start a self-test sequence of instructions issued from the PLA which will test the functionality of the majority of the registers, multiplexers, and data paths in the machine as well as test the majority of the arithmetic and logical functions which can be carried out by arithmetic and logic unit of the microprocessor. The control unit also contains logic to support an external bus arbiter for use of the computer in a multiprocessor network with a common bus.
