This invention involves a capacitor memory cell (C.sub.S) of, typically the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor (T.sub.1), and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) transistors (T.sub.2, T.sub.3) connected between the MOS capacitor and an A.C. refresh line which is independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor.
Depletion-mode FET (13a of 8) joins to enhancement-mode FET (13b of 8) to store charge capacitively as a memory cell. That enhancement-mode FET (13b of 8) is connected to an FET capacitor (19). When the memory stores a high charge, a refresh clock pulse on a line (21), passes the capacitor (19), turns off enhancement-mode part of joined FETs (8), and is effective to gate refresh switch (25) on. When the memory stores ground, the capacitor (19) is not activated and does not pass the refresh pulses. The memory requires very low power for refresh, and is compact and practical for use in large arrays.
A single-port memory cell arrangement includes a multiplicity of single-port memory cells, each having a selection transistor and a memory transistor. The selection transistor has a control terminal connected to a word line, and a load-path connected to a data line. The memory transistor has a control terminal connected to a supply potential, and a load-path connected to the second end of the selection-transistor's load-path. The memory transistor is configured to switch, in response to a signal on the data line, between first and second potentials corresponding to two memory states. These potentials and the supply potential are selected such that first and second ends of the memory-transistor-load-path are at the same potential. The memory cell also includes a controllable switch having a first terminal connected to a supply line, and a second terminal connected to the second end of the memory-transistor-load-path. A single charging device assigned to the single-port memory cells provides providing a precharging potential. From time to time, the charging device recharges a selected memory transistor through the supply line and a selected controllable switch corresponding to that memory transistor.
A dynamic memory cell is disclosed which provides means for rewriting the cell after reading without discharging the bit line driver to thereby improve cycle time. The cell includes an independently operated device to access the capacitive storage node to discharge the node of any charge thereon after the reading of a low or no charge bit on the capacitive storage node.
A dynamic memory cell comprises a storage transistor and an access transistor. The gate of the storage transistor is utilized as storage capacitor electrode, and is connected to its source by a high resistor. The drain of the storage is connected to a source of electrical potential (e.g., V.sub.CC). The access transistor connects the source of the storage transistor to a bit line. This arrangement multiplies the effective capacitance of the gate storage capacitor, reducing the area required and hence making the structure more compact than a typical inactive (one transistor) DRAM cell. In a preferred embodiment, the resistor is formed to overlie the storage transistor, and the drain of the storage transistor is connected to V.sub.CC by means of the sidewall of a trench formed in the semiconductor substrate.
The invention relates to a method for converting volatile memory cells to non-volatile memory cells with minimal modifications. There is included a volatile memory cell which is modified to permanently retain data by using one refresh port to transmit an active low voltage signal and configuring one terminal of the storage transistor to receive either an active high or low voltage signal.
