This invention concerns an analog-to-digital correlator with programmable coefficients with values of +1, -1 or 0. This correlator comprises a charge-transfer shift register to receive samples of the analog input signal for correlation, and two programmable digital-output shift registers, followed by memories to establish coefficients with values of +1, -1 or 0. Depending on the signal available at the digital register outputs: reading of charges is blocked on the analog register, corresponding to establishment of coefficient 0; reading of charges occurs, reaching either the positive or the negative input of a differential amplifier, corresponding to the establishment of coefficient +1 or -1.

In a spread spectrum communications system employing cyclic code shift keying as its primary modulation, the transmission waveform is spread for transmission security by modulo-2 adding a pseudo-noise sequence to the CCSK data symbols prior to phase modulating onto a carrier signal for transmission. If the transmission modulation is minimum shift keying (MSK) the two components of the data stream are applied to the carrier with a differential encoding step implicit in the modulation scheme. This differential encoding characteristic makes stripping of the PN spread function prior to CCSK demodulation difficult at the receiving end. In order to demodulate this waveform in an optimum manner, an array correlator, the adjacent correlator stages of which have one chip relative time displacements of their CCSK reference waveform, is employed. In effect the array correlator becomes a parallel array of matched filters matched to each cyclic shift of the incoming waveform. By modulo-2 addition of the PN spreading waveform with the time displaced CCSK reference waveform in each stage of the correlator, the correlator can be made to match all versions of the spread symbol being received.

An analog-digital correlator 10 utilizes a plurality of sample and hold cirucits 16-0 to 16-(M-1) to directly store samples of a received analog signal. Bits of a correlation pattern are shifted through stages in a correlation pattern shift register 26. The state of the correlation pattern bits causes the value in the associated sample and hold circuit 16 to either be inverted or noninverted when it is summed with other similarly generated signals from the remaining sample and hold circuits to form the correlation output sum by network 30. The output of network 30 will peak when the bits of the digital correlation pattern signal are shifted to stages in register 26 that are aligned with the sample and hold circuits containing the digitally-impressed code of interest. In the preferred embodiment, a mask shift register 28 is used to selectively disable certain of the sample and hold circuits from affecting the correlation output sum. To this end, mask bits corresponding to the length of the digitally-impressed code are shifted through mask register 28 simultaneously with the correlation pattern bits in register 26.

Briefly, in accordance with one embodiment of the invention, a programmable filter may implement an infinite impulse response filter so that a transceiver in which the filter is utilized may be programmable to operate in one or more modes in accordance with one or more communication standards. The programmable infinite impulse response filter may replace one or more analog filters of the transceiver so that a desired filter response may be programmed by a baseband processor. Delay functions of an infinite impulse response filter may be implemented using feedback and multiplexing.

Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.