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Description  |
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SUMMARY OF THE INVENTION
This invention relates to electronic organs and more particularly to a
capture combination action system used in an electronic organ.
Over the years a wide variety of systems have been developed for
controlling organ stops to permit the performer to change the stop
combination on the instrument including capture combination systems in
which the stop combination may be quickly changed to another previously
set combination by merely depressing a switch control, such as a thumb
piston or toe stud. In the conventional approach, when the thumb piston or
toe stud is depressed, the stop tabs to be activated by the particular
piston or toe stud in question are moved to the "on" state by either
purely mechanical or electro-mechanical means. Such movement not only
provides the obvious function of energizing the required stops, but the
"on" position of the stop tab also provides a visual indication to the
performer as to which of the stops have been energized. In this type of
capture system the operator can easily program or set any combination of
stops desired into any piston by manually turning on the appropriate
stops, and simultaneously holding the "set" piston and the piston or toe
stud into which the combination is to be programmed. With this
arrangement, the selected combination will then be activated whenever that
particular piston or toe stud is again depressed.
Capture combination systems of the character described have a number of
disadvantages, among which are cost effectiveness, speed of action, and
ease of operation. In the modern electronic organ the stop switches, which
are the ones directly controlled by the drawbar or stop tab mechanism,
control a minute amount of power, typically in the milliwatts range. By
contrast, the power supplied to the solenoid-activated draw knob or stop
tab mechanism to control the stop switch is in the tens of watts range.
Thus, tens of watts of power are required to control a few milliwatts of
power, which is an extremely inefficient arrangement from the standpoint
of the amount of power required to operate the system. In addition, the
system is expensive in terms of the cost of the solenoids used in the
mechanisms as well as the power switching electronics and power supply
required to drive the solenoids. Another major disadvantage of such
systems is their sluggish operation and the presence of mechanically
produced noise which can be of substantial magnitude when numerous stops
are simultaneously actuated.
Generally, each operational piston permits actuation of a selected group of
stops when that piston is actuated, thereby permitting selection of any of
a number of combinations of stops in accordance with actuation of the
corresponding ones of the pistons. The pistons generally are grouped in
various categories identified by their control capabilities. Divisional
pistons, for example, are associated with a corresponding division and
provide for control of only those voice stops and couplers associated with
that same division. Independent general pistons, on the other hand,
provide for control of a combination of all of the stops provided in the
organ simultaneously regardless of the relationship of groups of those
stops to specific divisions.
In general, combination systems include a memory for recording the
combination of stops associated with each piston. Upon actuation of a
piston, the combination system sets the corresponding stops as indicated
by the stored information in memory. Numerous techniques have been
proposed for combination system memories including mechanical linkages,
electrical bar-switches, and computer electrical memories. Preset
combination systems are those in which the memory is hard-wired so that
changes may be made only by rewiring a terminal located inside the
console. The stop combinations cannot be changed by the organist from the
front of the console. In a setter board system, a wire associated with
each stop is connected to a switch or jumper jack. A row of switches is
provided for each divisional piston so that the memory is set by moving
the switches to the desired on or off positions. Generally, a large number
of such switches is required in a setter board system.
A capture combination system permits the organist to set information into a
combination memory by means of the conventional organ controls. For
example, with regard to the swell division, a combination of stops is
selected which produces a desired tonal effect for each of the pistons of
that division. The stop combination information is then placed into memory
by depressing a set piston, and simultaneously pressing an available
piston of that division. Subsequently, whenever that divisional piston is
depressed, the stops of the preselected combination captured in the
operation with the set piston are turned on or set.
In U.S. Pat. No. 3,103,847, issued Sept. 17, 1963, to C. A. Raymond, a
capture-type combination action is described where the stop actuating
members are mechanically connected by means of complex mechanical linkages
to electro-mechanically operated solenoids which set or reset selected
combinations of stops.
A setter board arrangement is illustrated in U.S. Pat. No. 3,422,718,
issued Jan. 21, 1969 to R. G. Noehren. In this arrangement, a stop
combination setter determines the stop combinations for each piston in
accordance with a selected combination data storage media such as a patch
board, punched card or tape, magnetic card, etc. The stop tabs themselves
are actuated by electro-mechanical solenoids to provide a visual
indication to the organist of the stops that have been selected.
A more sophisticated setter board arrangement is illustrated in U.S. Pat.
No. 4,157,051, issued Jan. 5, 1979 to Peterson et al. This arrangement
uses specially constructed key tab switches biased to return to a neutral
position, which are depressed to set an electronic latch circuit, thereby
energizing an associated LED indicator mounted on the stop tab and turning
on the associated stop. Preset pistons toggle preselected latching
circuits to the ON position by means of diode gates preselected by a
matrix of separate toggle switches similar to a setter board system.
However, a desired combination of stops cannot be captured and set from
action of the stop tabs themselves with this arrangement.
U.S. Pat. No. 3,449,995, issued June 17, 1969, to O. W. Sepp, Jr., uses a
plastic or metallic preselector index card for programming the selected
stops. When the particular combination is called, the stop tabs are
physically moved to the ON position by means of electro-mechanical
solenoids.
In U.S. Pat. No. 3,498,168, issued Mar. 3, 1970 to T. W. Cunningham, the
stop combinations are stored in a magnetic core memory, and the stop tabs
are physically moved to the ON position by means of electro-mechanical
solenoids. A similar arrangement is shown in U.S. Pat. No. 3,686,994,
issued Aug. 29, 1972 to R. S. Badessa.
In U.S. Pat. No. 3,659,488, issued May 2, 1972 to R. Deutsch, the piston
and stop switches are scanned under control of a central processing unit
to detect actuation of individual ones of the pistons and associated
stops. This information is gated into a temporary memory, and eventually
stored in an external physical memory such as a magnetic card, punched
paper tape or cassette recorder. The information pertaining to the
selected combination must be read into the apparatus from the external
memory. The piston matrix is initially scanned at a relatively high speed,
with the information from each line of the stop matrix read out in
succession at a relatively low speed. The stop tabs selected are
physically moved to the ON position to provide a visual indication of the
selected stops.
A similar arrangement is illustrated in U.S. Pat. No. 3,926,087, issued
Dec. 16, 1975 to S. W. Griffis. In this arrangement, a piston closure
causes a central processing unit to select a particular preselected
combination of stops from a list contained in a read only memory. However,
a separate piston is required for each preselected stop combination
inasmuch as the combinations cannot be set from the stop tabs themselves.
Furthermore, when selected, the stops are physically moved to the
activated position by means of electro-mechanical solenoids.
The organ capture action of U.S. Pat. No. 4,006,658, issued Feb. 8, 1977 to
Kappes et al., uses a 23 channel recirculating shift register to store
information concerning the combination of stop tabs to be selected. The
stop tabs are physically moved to the activated position by means of
actuating coils multiplexed at a 60 Hz rate.
U.S. Pat. No. 4,157,049, issued June 5, 1979 by H. Watanabe, also utilizes
a shift register to store piston data. Activation of a particular piston
causes the programmed combination of stop tabs to be physically moved to
the activated position. This system also utilizes a crescendo control
which produces a digital code by means of a multiple pole switch to
address a crescendo registration memory for activating the appropriate
combination of stops and indicating lights.
The capture combination system of the present invention utilizes stop tabs
or stop controls of the momentary-acting type in which the organist
depresses the tab to turn on the stop, after which the tab automatically
returns to a center rest or neutral position. The organist turns the tab
off by deflecting the tab upwardly, after which the tab again
automatically returns to the center rest position. The tabs are thus moved
by the same motions that the organist uses with conventional detent-type
tongue tabs. When the tab is depressed to turn on the stop, an indicator
light adjacent the stop tab is turned on to give the organist a visual
indication that the stop is "ON", and the indicator light is extinguished
when the stop tab is momentarily moved to the "OFF" position.
Signal processing in the present invention is under the control of a
microprocessor unit operating from a control program stored in a read only
memory. All of the the controls associated with the musical instrument
such as stop tabs, thumb pistons, toe studs and the crescendo shoe, are
continually and sequentially scanned by the microprocessor unit. When one
of these controls is activated, this condition is sensed by the
microprocessor unit which provides suitable control outputs to the
particular stop circuits required by the function of the control
activated, and to the indicator circuits for providing a visual indication
of the stops selected.
This capture system permits the organist to easily program or set any
combination of stops desired. The information relating to the combination
of stops selected is stored in a random access memory under control of the
microprocessor unit. In addition, the stored information may be called as
desired from the random access memory by means of the pistons or toe studs
to set the desired combination of stops. It will be observed that a visual
indication is provided to the organist for the stops selected by means of
indicator lights, so that the stop tabs themselves are not physically
moved from the center rest position by the capture combination action.
Furthermore, the program stored in the read only memory contains a
debouncing program to insure that false switch closures caused by
mechanical bounce or the like do not cause erroneous indications or
selections of the organ voice circuits.
The present invention also uses a crescendo circuit which operates in
association with the crescendo shoe to control the execution of a
crescendo program stored in the read only memory, and consequently the
actuation of the stop combinations associated with each position of the
crescendo shoe. In the preferred embodiment described, the crescendo
circuit incorporates a delay circuit responsive to the setting of the
crescendo shoe, which causes an interrupt request to be delayed to the
microprocessor unit, and a count established proportional to the crescendo
shoe position. The magnitude of this count is compared with the values
assigned to various ones of the stops stored in a data table, resulting in
the stops having values associated with particular count values being
actuated. With the crescendo shoe in the closed position, the time delay
involved is short, causing the count value to be substantially zero so
that no stops are actuated. However, as the crescendo shoe is further
depressed, and the delay becomes greater, the count value increases
correspondingly, causing more stops to be actuated.
At the same time the crescendo stops are activated, a light indicator
associated with each stop tab produces an output to indicate that that
particular stop tab has been actuated. In addition, one or more crescendo
indicator lights are activated to provide an indication of the relative
position of the crescendo shoe. Consequently, the organist is provided
with two types of visual feedback relating to the crescendo function.
Further features of the invention will become apparent from the detailed
description which follows:
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1A-FIG. 1B is a block diagram of the processing circuitry of the
capture combination action of the present invention.
FIGS. 2A-FIG. 2E is a schematic diagram of a preferred implementation of
the capture combination action of the present invention.
FIG. 3 is a schematic diagram illustrating the manner in which the
individual drawings of FIG. 2A-FIG. 2E are to be assembled to complete the
diagram.
FIG. 4 is a schematic diagram illustrating an alternate embodiment of the
indicator and voice drive circuits of the present invention.
DETAILED DESCRIPTION
The capture combination action of the present invention is illustrated
generally in the block diagram of FIG. 1A-1B and more particularly in the
preferred implementation illustrated in FIG. 2A-2E. Signal processing in
the present invention is under the control of a microprocessor unit (MPU)
100 operating from a control program stored in programmable read only
memory (PROM) 200 and listed in detail in Appendix A and Appendix B. As
used herein, programmable read only memory or read only memory means
designates a physical device having permanently stored operating programs
or data. All of the controls associated with the musical instrument such
as stop tabs, thumb pistons, toe studs and the crescendo shoe, are
continually and sequentially scanned by MPU 100. When one of these
controls is activated, this condition is sensed by the MPU to provide
suitable control outputs to the particular stop circuits required by the
function of the control activated, and to the indicator circuits for
providing a visual indication of the stops selected.
As noted above, the capture system permits the operator to easily program,
or set, any combination of stops desired. This information relating to the
combination of stops selected is stored in random-access memory (RAM) 500,
under control of MPU 100. In addition, the stored information may be
called as desired from RAM 500 to set the desired combination of stops. As
used herein, random access memory or random access memory means designates
a read/write memory.
In the preferred implementation illustrated in FIGS. 2A-2E, MPU 100
comprises an eight bit microprocessor such as the Mostek 3850 CPU. The
manner in which the individual drawings of FIG. 2A-FIG. 2E are to be
assembled to complete the diagram is illustrated in FIG. 3. In the
arrangement illustrated, I/O port zero comprising I/O bus lines
I/O.sub.00-07 are used for transfer of latch information. The I/O port one
lines I/O.sub.10-17 are used as the switch-latch address output port
lines. All of these functions will be described in more detail
hereinafter.
A system clock 101, which may be conventional in design, operates at 1.95
MHz.+-.50 KHz to supply clock signal XTLY to MPU 100.
MPU 100 communicates over data bus lines DB.sub.0-7 with static memory
interface 300, which may comprise a Mostek 3853 static memory interface
module. This device provides interface logic for static read/write
memories which do not need to be refreshed. Data bus lines DB.sub.0-7 are
also connected to the data output terminals O.sub.1-8 of programmable read
only memory (PROM) 200 which contains the operating program for MPU 100 as
will be described in more detail hereinafter, and may be implemented as a
53255 ROM.
The control bus connected between MPU 100 and static memory interface 300
comprises a number of control lines ROMC.sub.0-4, 0, WRITE, and INT REQ,
which control transfer of information between MPU 100 and the static
memory interface, as well as the various memory devices.
A crescendo circuit 400 is connected between the interrupt control bit
output ICB from MPU 100 and the external interrupt line input EXT INT of
static memory interface 300. This circuit operates in association with the
crescendo shoe to control the execution of the crescendo program stored in
PROM 200, and consequently the actuation of the stop combinations. As
shown in FIG. 2E, the ICB signal from MPU 100 is coupled through resistor
R1 to the base of transistor Q1. The emitter of transistor Q1 is connected
to ground, while the collector is connected through the parallel
combination of resistors R2 and R3 to the emitter of transistor Q2, as
well as to the junction of capacitor C1 and resistor R4. The remaining
terminal of capacitor C1 is connected to ground. The base of transistor Q2
is connected through the parallel combination of resistors R5 and R6 to
supply voltage +V.sub.1, and through resistor R7 to ground. The collector
of transistor Q2 is connected through resistor R8 to the base of
transistor Q3, and through resistor R9 to ground. The emitter of
transistor Q3 is connected to ground, while the collector is connected
through resistor R10 to supply voltage +V.sub.1, and to the EXT INT input
of static memory interface 300, to form the output of crescendo circuit
400.
The remaining end of resistor R4 is connected to one of the fixed terminals
of variable resistor R11, which is associated with the crescendo shoe. The
other fixed terminal of resistor R11 is connected to the base of
transistor Q4. The wiper terminal of variable resistor R11 is connected to
the collector of transistor Q5 and is mechanically linked by means not
shown to the crescendo shoe. It will be understood that as the crescendo
shoe is activated, the wiper of variable resistor R11 is caused to move,
thereby varying the resistance applied between the base and collector of
transistors Q4 and Q5, respectively. The emitter of transistor Q5 is
connected through resistor R12 to supply voltage +V.sub.2, while the base
is connected to the emitter of transistor Q4, and through resistor R13 to
the same supply voltage. The collector of transistor Q4 is connected
through resistor R14 to supply voltage +V.sub.1.
Initially, the ICB line from MPU 100 is at a high level, causing transistor
Q1 to be turned off and discharging capacitor C1. However, when ICB goes
low, transistor Q1 is cut off, permitting capacitor C1 to charge through
constant current source Q4, Q5, crescendo shoe control resistor R11, and
resistor R4. The position of the crescendo shoe determines the resistance
of variable resistance R11 and the degree to which capacitor C1 charges
during the time period defined by the ICB signal. The charge on the
capacitor is applied to the emitter of transistor Q2 whose base voltage is
determined by the resistor divider formed by resistors R5, R6 and R7.
With the crescendo shoe in the closed (fully up) position, potentiometer
R11 is adjusted to set the voltage on capacitor C1 at a value which is
more negative than the transistor Q2 base bias. In this mode of operation,
transistor Q2 remains cut-off and no EXT INT command is applied to static
memory interface 300. As the crescendo shoe is depressed from minimum to
full, thereby varying resistor R11, the rate of charge on capacitor C1
increases accordingly. After a time period determined by the crescendo
shoe position, the emitter-base junction of transistor Q2 becomes forward
biased, permitting this transistor to saturate, thereby producing a signal
which is inverted by transistor Q3 and applied to the EXT INT input of
static memory interface 300. Consequently, the EXT INT signal will occur
at some delayed time following the initial transition of each ICB pulse.
The EXT INT signal produced by crescendo circuit 400 causes an interrupt
request INT REQ to be produced by the static memory interface 300, thereby
causing microprocessor unit 100 to respond to the interrupt request by
executing the crescendo program stored in PROM 200 as will be described in
more detail hereinafter. This program establishes a count proportional to
the crescendo shoe position. The magnitude of this count is compared with
the values assigned to various ones of the stops and stored in a data
table. Those stops having values associated with particular count values
are actuated. With the crescendo shoe in the closed position, the time
delay between the ICB and EXT INT signals is short causing the count value
to be substantially zero, such that no stops are actuated. However, as the
crescendo shoe is further activated, and the delay becomes greater, the
count value increases correspondingly, causing more stops to be actuated.
It will be observed that this technique permits the interrupt request to
MPU 100 to be delayed as a function of the crescendo shoe setting. It will
be understood that other ways of accomplishing this delay, including
digitally implemented delay lines and the like, may be substituted as
desired. It will be further understood that the crescendo circuit 400
could operate to produce a digital sequence for causing the aforementioned
count to be established as will become apparent from the description which
follows.
In FIG. 2A the address bus formed by address lines A.sub.0-8 connects
static memory interface 300 with PROM 200, while address lines A.sub.0-9
connect static memory interface 300 with RAM 500. For purposes of an
exemplary showing, RAM 500 comprises an AMI 6508 static CMOS RAM with
1024.times.1 bit capacity. However, it will be understood that other types
of mass memory media may be used as desired within the inventive concept
of the present invention. Data is read into or out of RAM 500 under
control of the chip enable CE line originating from memory address decoder
600 and the read/write R/W signal originating from static memory interface
300.
When the CE line is low, data is read into RAM 500 from line DB.sub.7 of
the data bus according to the address present on the address bus lines
A.sub.0 -A.sub.9, if the R/W line is in the low state. Likewise, when the
CE line is in the low state, and the R/W line is in the high state, data
will be read from the designated address location of RAM 500 through the
D.sub.OUT terminal onto data line DB.sub.7 of the data bus through
parallel connected bilateral switches A and D. Switches A, B and D may be
implemented by 4066 bilateral switches. These switches are turned on to
provide a transmission path when the CPU READ line, which is also
connected to the CHIP SELECT C.sub.S inputs of PROM 200, is at a high
level.
As is well understood in the art, RAM 500 may include a continuously
charged NiCad battery supply to insure that the stored information is
preserved when the organ is disconnected from a power source, or under
conditions of power failure.
Memory address decoder 600 decodes static memory interface 300 output bits
A.sub.10, A.sub.11, A.sub.12, and A.sub.14 to provide the BCD address for
RAM selection. Memory address decoder 600 may be implemented as a 74LS42
BCD to decimal decoder which produces a logical zero at the output
corresponding to a four bit binary input from zero to nine, and a logical
one at the other outputs. Since in the implementation illustrated, the
selection address is part of the RAM output address, the A.sub.14 bit is
slightly delayed by means of a delay network, composed of resistors R15,
R16 and R17, and capacitor C2. In other words, delay of the A.sub.14 bit
causes the CE signal to be delayed by an amount sufficient to permit the
addressing inputs for RAM 500 to stabilize. Output O.sub.1 from memory
address decoder 600 is connected to the chip select inputs C.sub.S1 and
C.sub.S2 of PROM 200 to enable this memory device when the proper address
is decoded by the memory address decoder. In addition, output bit O.sub.9
of memory address decoder 600 is connected through switch B to form the
chip enable CE signal for enabling RAM 500.
The capture combination action circuit of the present invention also
includes an initialization circuit, indicated generally at 700. This
circuit prevents RAM 500 and MPU 100 from being energized until the system
power supplies have stabilized at initial power turn-on. Initialization
circuit 700 comprises resistors R18 and R19, and capacitor C3 serially
connected between supply voltage +V.sub.1 and ground. The base of
transistor Q6 and the emitter of transistor Q7 are connected to the
junction of resistors R18 and R19. The emitter of transistor Q6 is
connected to ground, while the collector is connected to the cathode of
diode D1 and the external reset EXT RES input of MPU 100. The collector of
transistor Q7 is connected to the anode of diode D1, and to the junction
of resistors R20 and R21, which are serially connected between supply
voltage +V.sub.2 and ground.
When the organ power is initially switched on the charging current for
capacitor C3 develops a voltage drop across resistor R19. When this
occurs, transistor Q6 satur | | |
