A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radicies selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input data state satisfying a selected count-qualifier state condition.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a division of an earlier filed copending application of the same inventors and assignee, Ser. No. 828,138, filed Aug. 29, 1977, abandoned in favor of a continuing application Ser. No. 75,787 filed on Sept. 17, 1979, which in turn was abandoned in favor of a continuing application Ser. No. 210,462 filed on Nov. 25, 1980.
A microcomputer includes addressable functional blocks and an internal state latch coupling an A/D converter to an internal bus. A programmable selector is coupled to the address bus and controls the latch to latch data when a selected address is generated on the address bus to that the latched data is provided as an external analog signal for monitoring.
Ongoing succession of states occurring in a collection of digital signals is monitored by a logic state analyzer which stores either all such states or a selected subset thereof meeting certain qualification criteria. The memory into which the states are stored is updated with oldest stored states being overwritten as the newest states are stored, the collectivity of which may be termed a captured trace. The above-mentioned qualification and sequential criteria are termed a trace specification. The utility of such a trace in a logic state analyzer is enhanced by allowing the user to divide the collection of digital signals into groups of related signals, assign symbolic labels to the groups, and indicate a radix for each group. Such division, assignment and indication may be termed a format specification. Subsequent trace specifications as well as the displayed or printed form of the trace itself then incorporate the format specification.
A circuit detects that a plurality of signals are generated in a predetermined sequence. The plurality of signals are applied to address terminals of a memory which has stored therein a predetermined pattern, and a divide-by-N counter (N:positive integer) counts a first data output signal from the memory N times and applies a carry output signal generated as a result thereof to another address terminal of the memory. An output signal of the circuit is derived from a second data output terminal of said memory when the plurality of input signals occur in the predetermined pattern of the memory and the carry signal from the counter is applied to the memory.
A logic analyzer is disclosed which displays at least an input logic signal on a cathode ray tube, controls a cursor position on the cathode ray tube and obtains a relationship between a predetermined phenomenon included in the input logic signal and the cursor position. In a search mode, the predetermined phenomenon is a search word or a glitch. In a compare mode, the predetermined phenomenon is a reference logic signal.
Apparatus is disclosed for testing an electrical circuit by means of signature analysis. Responses to a sequence of test patterns from the circuit under test are supplied to a linear feedback signature register (LFSR) which produces a signature signal at its output representing its current state in dependence upon its prior state and the received response signal. A programmed read-only-memory is addressed by these state signals of the LFSR and produces, at its output, a logical "1" signal if the current signature represents a permissible state of the LFSR and a logical "0" if the state is not permissable. This checking occurs throughout and during the testing sequence in contrast to conventional signature analysis wherein the comparison only occurs at the end of the testing sequence.
