This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.
A serializer/deserializer for a flow of n-bits of data shifted according to the rate of a clock includes an n-rows and n-columns matrix of 1-bit registers (00-77). Each 1-bit register is connected through its input to a first switch connected to the output of the register in the same row and lower rank column and to a second switch connected to the output of the register in the same column and upper rank row. Input terminals (E0-E7) are connected to the registers of the lower rank column and of the upper rank row. Output terminals (S0-S7) are connected to the registers of the upper rank column and of the lower rank row. The matrix cells are arranged according to a triangle, the cells being arranged one with respect to the other according to the structural corresponding to folding a square matrix along its diagonal.
