Compensation for the current flowing in the collector resistance of a transistor is achieved by generating a compensating current of appropriate magnitude and polarity sense, and applying that compensating current to the base of the transistor. To this end, a voltage equivalent to that across the transistor emitter-collector path is applied across a current conductive device representative of the collector resistance. The current therethrough is then proportioned by a current amplifier and applied to the base of the transistor to be compensated.
Two compensating resistors in a mirror bias circuit coupled to a radio frequency (RF) amplifier are configured such that transistor base-emitter voltages are adjusted to stabilize RF transistor quiescent current for variations in collector voltage, Vcc. For example, when battery power is drained during device use, Vcc decreases. As Vcc decreases, less current is drawn through the compensating resistors, thereby decreasing the voltage drop across the compensating resistors and increasing the transistor base-emitter voltages in the mirror bias circuit and the radio frequency (RF) amplifier. Thus, the tendency of the RF transistor quiescent current to decrease as Vcc decreases is off-set because the compensating resistors cause an increase in the RF transistor base-emitter voltage, thereby increasing quiescent current. In one embodiment, the first compensating resistor size is equal to the second compensating resistor size multiplied by the ratio of the buffer transistor current rating to the mirror transistor current rating.
An embodiment to mirror current having a pair of current mirroring transistors and a pair of cascode transistors coupled to the current mirror transistors, and furthermore having an amplifier to provide an offset voltage between the drain of a cascode transistor and the gate of a current mirror transistor, where the drain of the current mirror transistor is connected to the source of the cascode transistor, and where the amplifier buffers the gate of the current mirror transistor from the drain of the cascode transistor. Other embodiments are described and claimed.
A current mirror circuit is disclosed including a reference device and a biased device, each having control, input and output elements, with the control element of the biased device operably connected to the control element of the reference device. A reference current source is connected to the input element of the reference device and produces a reference current flowing through the reference device, wherein a bias current is produced in the biased device as a multiple of the reference current. A compensation network is connected between the biased device and the reference device for maintaining a constant bias current in the biased device regardless of varying operating characteristics in at least one of the biased device and the reference device.
A current mirror circuit comprising a first current mirror circuit with a first error correction transistor connected between the base and collector of the first transistor of the first current mirror; a second error correction transistor connected to the first error correction transistor and a second current mirror circuit connected to an input current source and the base of the second error correction transistor. The second error correction transistor samples the signal from the collector of first error correction transistor and feeds its base current, which is almost equivalent to the base current of the first error correction transistor, to the input of the second current mirror circuit. The second current mirror circuit combines the input current source current with the base current of the second error correction transistor and generates a current which is fed to the collector of the first transistor of the first current mirror circuit. The value and polarity of the current is such as to offset the base error current of the first error correction transistor, thus improving the relationship of input current to output current of the first current mirror circuit by a factor of .beta.+1. This improvement is especially significant when using lateral PNP transistors which typically have very low betas.
A radio frequency (RF) amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, includes first, second, and third transistors interconnected in a modified current source or current mirror configuration with first, second, and third resistors and a matching circuit to produce a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal. Implemented with bipolar transistors, enhancement mode field effect transistors, or depletion mode field effect transistors, the circuit achieves two-stage amplification with simplified interstage coupling and therefore fewer components and less size and cost.
