A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive approximation when converting.
An integrated circuit for a disk drive that includes a sucessive-approximation analog-to-digital converter (ADC) with a two-stage digital-to-analog converter (DAC) and may also include a servo demodulator. The circuit may be implemented in a basic or pure-digital CMOS chip because the ADC includes no precision analog elements such as resistors and capacitors. The first DAC stage operates on the most significant group of bits, and the second DAC stage operates on the least significant group of bits. The DAC includes a reference current source. The first DAC stage is a multiplying DAC that multiplies the reference current in response to its digital input, and the second stage is a dividing DAC that divides the reference current in response to its input. The DAC also includes a current summer, such as a resistor, that receives the output current of each stage and provides the voltage that corresponds to the sum of the currents to a comparator. The comparator output controls a successive-approximation register. The circuit of this invention is suitable for use in implementing an Area Integrating Servo Demodulator (AISD) for detecting head position information in a disk drive servo signal without precision analog components.
An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each transmission gate 36 has a channel width with some predetermined proportional relationship to the channels of input transistors 12 and mirroring output MOS transistors 14 to 44 with the input transistor 12 connected to a constant current source, the total output mirroring current of the output mirroring transistors is in quantised analog form and varies according to the cumulative currents from the mirroring MOS transistors as the transistors are activated. The invention may be embodied in linear multiplying, non-linear and companding converters.
A digital switch module for a time division digital switching system includes an encoding law conversion memory and a control memory. The encoding law conversion memory has previously stored therein conversion data for converting between different types of encoding laws. For example, the A-law and .mu.-law encoding laws set forth in CCITT Recommendation G.711 can be converted by a digital switch module according to the present invention. The encoding law conversion memory includes a read only memory having regions for conversion between A-law and .mu.-law encoded data and for nonconversion of both A-law and .mu.-law encoded data. The control memory designates which of the regions in the encoding law conversion memory is to be used during each time slot, thus dynamically controlling whether data passing through the digital switch module is converted or not. The type of conversion or nonconversion designated by the control memory can be determined by the type of data, e.g., digitized voice signals may require conversion but non-voice signals will not be converted, and the channel path of the data, for example from an A-law encoded system to a .mu.-law encoded system.
Digital-analog converter intended to convert into analog signals digital signals formed of sign bits, of step bits and of segment bits, particularly signals coded by data compression according to law A, the said converter comprising a sign generator (4), intended to receive the sign bit of the said digital signal, a step generator (7), connected to the output of the sign generator and intended to receive the step bits of the said digital signal and to a segment generator (8) connected to the step generator and intended to receive the segment bits of the said digital signal, characterized in that the segment generator (8) is connected to the sign generator by means of the step generator (7) only.
Pulse Code Modulation (PCM) translator for translating a PCM input word into a PCM output word, one of said words being in accordance with a compressed code and the other with a linear code, characterized in that it is adapted to convert the binary bits of the input word into those of the output word in accordance with either the A-law or the mu-law. The circuit forms part of a telephone line circuit (LC) connected between a telephone line (LI) and a digital switching network (SNW) and comprising the cascade connection of a subscriber line interface (SLIC) able to perform line control and supervision, a digital signal processor (DSP) mainly adapted to execute analog-to-digital and digital-to-analog conversion operations, the above transcoder circuit and a dual processor terminal controller (DPTC) which deals with the general control of the line circuit. The DSP only processes linear PCM signals, whereas the DPTC solely operates on companded PCM signals.
