The disclosure concerns a capacitive network and also concerns the individual metal layer carrying dielectric layers of which the capacitive network is comprised. Each dielectric layer is comprised of a flat plate having one or two rows of metal layers printed on one surface of it. At least one or perhaps both of the opposite edges of the dielectric layers are formed with grooves or incisions that define respective electric contact areas. There is a respective row of metal layers on the dielectric layer for each edge with grooves. Each metal layer is shaped to have a respective lead portion that extends toward a respective adjacent groove. The lead portions from the metal layers extend toward a first set of alternate grooves, leaving the second alternate set of contact areas not receiving an electric lead of that dielectric layer. Two dielectric layers are overlaid so that their respective rows of metal layers are in overlapping relationship but the dielectric layers are oriented so that metal layers on adjacent dielectric layers are always separate by a layer of dielectric material. The positions of the metal layers on one cooperating dielecetric layer are staggered along the length of the respective dielectric layer with respect to the positions of the metal layers on the adjacent dielectric layer, so that the leads of the metal layers on the adjacent dielectric layer extend toward the second set of alternate grooves, toward which the leads from the metal layers of the first dielectric layer did not extend. Electric diodes may be electrically connected between the grooves, whereby the diodes are connected in series along the grooves.
Integrated voltage multiplier constructed by multilayer technology in the form of a homogeneous block constituted by a stack of thin ceramic dielectric sheets metallized in such a way that each sheet carries metallized zones constituting the foils of capacitors, certain of which are connected in series. Thus, the block has at least two groups of series-connected capacitors. A recess is provided in the block between the two groups for the diodes interconnecting the capacitors of the two groups.
A ceramic multilayer capacitor array having a plurality of capacitors in a surface mount compatible package. The array is constructed from a plurality of first dielectric plates, each of which has a first pattern of electrodes, and a plurality of second dielectric plates, each of which has a second pattern of electrodes. The second pattern of electrodes is substantially identical to the first pattern of electrodes, and is shifted with respect to the first pattern of electrodes. Each of the electrodes has at least one tab portion, which extends to at least one of the side faces of the package. Perpendicularly projecting first and second plates, the tab portions of the electrodes in the first plates are free from the tab portions of the electrodes in the second plates.
A capacitor array in which a plurality of inner electrodes are formed so as to be overlapped with each other in the thickness direction while being separated by a ceramic layer in a ceramic sintered body to construct a plurality of capacitor units, and the plurality of capacitor units are separated from each other by a layer having a lower dielectric constant than that of ceramics composing the sintered body.
A monolithic multiple ceramic capacitor is made by interspersing layers of green tape containing ceramic powder in a binder with printed layers of electrical conductors, then compressing the layers and heating them to sinter the ceramic powder. Edge connections link the conducting layers in predetermined patterns to provide external connections to the capacitors. Use of parasitic or stray capacitance between pairs of external terminals provides additional useful values of capacitance. Unwanted stray capacitance between adjacent terminals is reduced by making slots by saw cuts or the like in either the green tape or the sintered material. Unwanted stray capacitance between elements inside the capacitor is reduced by ground planes between layers of capacitors and by layers of ceramic materials having relatively low dielectric constants to separate layers of capacitors, to form exterior layers of insulating material, or both.
