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Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology
   
Document Number
US Patent 4313177
Issued Date
January 26, 1982
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Abstract
Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.
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Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology - US Patent 4313177 Drawing
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Number of Claims:
6
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Published
January 26, 1982
Application Number
06/147,997
Filed
May 12, 1980
US Classification
365/174   365/203 365/210
Int'l Classification
H01L   27/02   (20060101)   G11C   11/413   (20060101)   G11C   11/4063   (20060101)  
Attorney/Law Firm
Priority Data
Oct 29, 1979 [DE] 2943565
USPTO Field of Search
365/174   365/203   365/210  
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