A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes detection apparatus for detecting a conflict condition resulting in an improper assignment. The detection apparatus, upon detecting such a condition, advances the relacement circuits forward for assigning the next sequential group of locations or level inhibiting it from making its normal location assignment. It also inhibits the directory circuits from writing the necessary information therein required for making the location assignment and prevents the information which produced the conflict from being written into cache store when received from memory.
Individual multi-cycle statements or complex arithmetic units such as dividers, multipliers and adders are replaced with a fast, single-cycle cache lookup. This cache contains the results of a specific arithmetic operation using specified operands. These operands were previously utilized by the processor to perform an earlier, but duplicative, operation. Before performing a specific arithmetic operation, the cache is referenced to determine if the operation has been performed. If the operation has been performed, the result is output without the need to perform the multi-cycle arithmetic operation. Preferably, the operands of the arithmetic operation are hashed to form an index to perform a cache lookup. If the portion of the cache indicated by the index registers a "hit", the stored arithmetic result is output. When a cache miss occurs, the arithmetic operation is completed by the arithmetic unit. The result may then be stored in the cache indexed by the operands.
The present invention relates to a timing error information managing system. This system comprises a timing error information file, a circuit information file, a correlating section for establishing a correlation between each of timing errors in the timing error information file and each of circuit configurations in the circuit information file, and for adding a circuit information pointer to the timing error information file and further for adding an error information pointer to the circuit information file, and a managing section for managing information on timing errors through the use of the circuit information pointer and the error information pointer. This configuration allows high-efficiency management of the timing error in formation, thereby achieving the speed-up of various kinds of processing using timing error information.
A cache location selector selects locations in a cache for loading new information using either a valid chain, if not all locations already contain valid information, or a history loop otherwise. The valid chain selects the "highest" location in the cache which does not already contain valid information. The history loop selects locations in accordance with a modified form of the First-In-Not-Used-First-Out (FINUFO) replacement scheme. Both the valid chain and the history loop are fully and efficiently implemented in hardware. During normal cache operation, both the valid chain and the history loop continuously seek an appropriate location to be used for the next load. As a result, that location is preselected well before the load is actually required.
A cache storage apparatus used for a plurality of requestors includes a unit for detecting if consecutive requests by the same requestor have the same access line; a stack unit for storing access addresses to a cache storage unit for each requestor after a cache directory unit was searched; and a plurality of pipe lines allowing the service of plural and concurrent accesses to other than the cache directory unit. In the cache storage apparatus, if there are consecutive accesses to the same line from the same requestor, the access address to the cache storage unit for the succeeding request is not obtained by searching the cache directory unit, but the access address to the cache storage unit for the preceding request is read from the stack unit and used as the access address for the succeeding request. If there is an access request from another requestor while processing the succeeding request which does not require the search of the cache directory unit, the priviledge of using the cache directory unit is given to the access request by the other requestor to thereby allow concurrently processing a plurality of requests.
The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class addressing controls are modified to change the distribution of cache contained data more uniformly among the congruence classes in the cache (by comparison with conventional cache class distribution). The cache addressing controls change the congruence class address as a function of the state of a higher-order bit or field in any CPU requested address.
