Each bistable cell of a memory matrix is uniquely accessed through a row transistor and a column transistor connected in series between one node of the bistable cell and the data-in. During WRITE, a single row is accessed activating all of the gates on the row transistors of that row, and a single column is accessed activating all of the gates on the column transistors of that column. Only the addressed cell at the intersection of the accessed row and column has both the row and column transistors turned on establishing a conductive path to the data line. All of the remaining cells on the accessed row and column have only one of their access transistors turned on. The other access transistor of these partially accessed cells remains non-conductive. The data-in on the data line is either high ("1") or low ("0") driving the addressed cell into one of two storage states. During READ only the addressed cell at the intersection of the accessed row and column has a conductive path to the high read voltage on the data line. The storage state of the addressed cell causes the data line voltage to either load down or to remain high. Write and read disturb are prevented because all of the remaining cells have at least one of their two access transistors turned off. The write and read isolation reduces the cell stability requirement to a very small trickle current necessary to maintain the node capacitance in the cell. The charge on these capacitances may be replenished periodically by charge pumping the load device. Read disturb of the accessed cell is avoided by employing a regenerative sense amplifier which restores the accessed data after each read cycle.
A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighboring modules and outputs thereto (XOUTN, XOUTE, XOUTS, XOUTW), only one of which is enabled by one of four selection signals (SELN, SELE, SELS, SELW) acting both on transmit path logic (20) and on receive path logic (21) in a return path. Each module includes configuration logic (22) which decodes commands providing the selection signals (SELN, etc), a READ signal and a WRITE signal. The configuration logic (22) is addressed when a bit is presented thereto by the transmit path simultaneously with assertion of a signal (CMND) which is supplied globally to all modules. The address configuration logic clocks the bit along a shift register and the selected command is determined by the position of the bit at the time that the global signal (CMND) is terminated. Each module includes a memory unit (23) including a free running address counter. When the WRITE command appears a data stream on the transmit path is read into the memory. When READ appears, the contents of the memory are read out onto the return path. Memory refresh occurs conventionally under control of the free-running address counter. In order to avoid heavy current in any of the power distribution conductors on the wafer, the count cycles of the free-running address counters are staggered.
A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.
