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Protection apparatus for multiple processor systems
   
Document Number
US Patent 4320450
Issued Date
March 16, 1982
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Abstract
In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input signals to the interface structure. The interface structure then translates those signals into an attention flag signal and signals identifying the source or nature of the emergency. The firmware engine then responds to those signals and effects the necessary measures to protect the data relative to the affected CPU.
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Protection apparatus for multiple processor systems - US Patent 4320450 Drawing
Drawing from US Patent 4320450
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Number of Claims:
9
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Owner
Honeywell Inc. (Minneapolis, MN)
Published
March 16, 1982
Application Number
06/089,493
Filed
October 30, 1979
US Classification
711/149   711/154
Int'l Classification
G06F   11/00   (20060101)   G06F   13/18   (20060101)   G06F   13/16   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
364/2MSFile   364/9MSFile   365/228   371/13   371/66  
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Description
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