A static Random-Access-Memory having a single bit line between each pair of adjacent columns of memory cells, implemented in a self-aligned, N-channel, silicon-gate system. Resistor element load devices are made in second-level polycrystalline silicon by an ion implant step. The second-level polycrystalline silicon is insulated from the first-level polycrystalline silicon by a multiple oxide insulation layer. An additional word line for each row of memory cells provides differentiation between adjacent memory cells sharing a single bit line.
A semiconductor memory device includes a gate region of each driver transistor arranged obliquely with respect to a first direction of a chip; a source/drain region of each driver transistor arranged obliquely with respect to the first direction; contact windows arranged substantially straight with respect to the first direction and connecting each source/drain region of the driver transistors to a power supply line provided in the first direction; and contact windows arranged every one contact window in a zigzag manner with respect to the first direction and connecting each source/drain region of transfer gate transistors to a corresponding bit line. By the constitution, it is possible to reduce an area of memory cell regions resulting in a reduction in a chip area, and to cause respective driver transistors to have uniform characteristics and thus improve an operation reliability thereof.
A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.
A static random access memory device including resistance loaded flip-flop circuits has adjacent memory cells arranged to form memory cell pairs. Each memory cell pair has a first unit cell and a second unit cell. Load resistors for the first unit cells and load resistors for the second unit cells are formed on different insulation layers and are stacked on each other on the substrate. A structural pattern of the load resistors is extended over adjacent memory cells in order for the length and resistance of the resistors to be increased. The length of the load resistors can be cut down for compensating for the increase in the resistance enabling the reduction in size of other devices, and enabling the packing density of the device to be increased.
A single polycrystalline silicone configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.
A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.
