An incoming a-c signal, whose amplitude is to be measured, successively passes through several decadic attenuator stages settable by respective cascaded decadic stages of a reversible counter. The attenuated signal is rectified and its voltage, or the RMS value thereof obtained from a squarer, gives rise to a calibration current, opposed by a constant reference current, for charging a capacitor of a current/frequency converter with a resulting current corresponding to their difference. Two threshold detectors in that converter, responding to a capacitor charge of either polarity beyond a predetermined limit, trigger a monoflop which fully or partly discharges the capacitor and steps the counter forward or backward as determined by a polarity sensor connected across the capacitor. A retriggerable second monoflop, responsive to the trailing edge of each stepping pulse, enables the second-lowest counter stage to be stepped out of turn when these pulses follow one another at high rate. The readings of the counter stages are also fed to a digital/analog converter working into a decibel meter.
A digital, high-voltage meter device is comprised of two poles, each having a probe connected to high-voltage resistors. The resistors are connected to supply low-voltage inputs to a digital voltmeter. In a modification, one of the poles including its probe and high-voltage resistor, is replaced by a connector, such as an alligator clip, adapted to be releasably connected to system ground.
A circuit for driving a display device having n display elements, where n is a positive integer greater than one, comprises a device for poviding a repetitive digital signal having a predetermined sequence of n digital values. The digital signal is converted to analog form in accordance with a predetermined transfer function and the resulting analog signal is compared with a second signal. A display enable signal is generated in the event that the magnitude of the analog signal bears a predetermined relationship to the magnitude of the second signal. A decoder circuit has a plurality of output terminals at which n distinct output signals, corresponding respectively to the n digital values, can be provided. The decoder circuit is responsive to the display enable signal for providing one of the n output signals when it receives the corresponding one of the n digital values.
