In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having "1" set in the bit position corresponding to the receive program. On the basis of the above described bit position, the receive OS specifies a receive program and informs the receive program of that fact. The receive program reads a message from the communication buffer. Communication between the send program and the receive program is thus realized. A send instruction and a receive instruction respectively for exclusive use of sending and reading out a communication ID are prepared beforehand.

The present invention is directed to a multi-port memory device responsive to two systems. The device includes an array of memory cells each represented by a unique row and column address. The memory device has first and second input/output ports and an input/output control circuit, responsive to the first and second input/output ports, for writing data into and reading data of the array. The device further includes a first signal decoder responsive to the first system for producing first signals for accessing a cell within said array. The device also includes a second signal decoder responsive to the second system for producing second signals for accessing a cell within the array. A control circuit is responsive to the first and second systems for identifying which of the systems is entitled to access to the array in the event both systems seek access to the same address at the same time. The address and data associated with the address from the system not having access are saved so that the operation can be performed when access is granted.

A data processing system includes at least two processors, each having a cache memory containing an index section and a memory section. A first processor performs a task by deriving internal requests for its cache memory which also may respond to an external request derived from the other processor which is simultaneously processing a task. To avoid a conflict between the simultaneous processing of an internal request and of an external request by the same cache memory, one request may act on the other by delaying its enabling or by suspending its processing from the instant at which these requests are required to operate simultaneously on the index section or the memory section of the cache memory of the processor affected by these requests. Thereby, the tasks are performed by the system at an increased speed.

A memory access selection circuit including a microprocessor, address, data and control multiplexers, a random access memory, storage circuits and related logic circuitry. This circuit allows both an external processor and the microprocessor to receive data from and transmit data to, the random access memory. The microprocessor controls access of the external processor to the random access memory by controlling and monitoring the multiplexer and storage circuits. This prevents erroneous data, address and control signals from appearing at the memory when switching between the microprocessor and the external processor as sources to the memory.

A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.