A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.
There is provided an analog-to-digital conversion technique that utilizes a sample and hold circuit for each bit try stage whereby after the most significant bit try, the remainder is sampled and held by the succeeding stage as an unknown input voltage for comparison with its respective reference voltage representing its corresponding bit weight. Thus, remainders for each bit weight comparison are successively passed from the most significant bit to the least significant bit as input voltages to the next bit try stage. The previous bit stage takes a new sample input voltage and starts another conversion at the next clock pulse. After the first full digital output of the initial conversion, a new digital output word of the successive sampled signal voltage is available after each clock pulse.
An improved signal processing apparatus for adjusting the .gamma.-characteristic of video signals, in which the .gamma.-correction is conducted either in a process of converting analog video signals into digital signals, or in a signal processing at charge level on the image charge signal formed in the image pickup element.
A pipelined analog-to-digital (A/D) converter includes a signal charge-coupled device (CCD) pipeline formed by stages for passing analog signals therethrough, and a plurality of reference CCD pipelines each for passing reference signals therethrough. A plurality of comparators are provided for comparing output analog signals from the stages of the signal CCD pipelines with respective output signals of the reference CCD pipelines. An encoded digital signal is obtained in accordance with the output signals of the comparators.
A microcomputer includes addressable functional blocks and an internal state latch coupling an A/D converter to an internal bus. A programmable selector is coupled to the address bus and controls the latch to latch data when a selected address is generated on the address bus to that the latched data is provided as an external analog signal for monitoring.
In a semiconductor device, one ends of capacitors connected via switching elements to multiple-input terminals, the other ends of the capacitors being connected in common to an input terminal of a sense amplifier. A first power source is provided for supplying a power to the switching elements, and a second power source is provided for supplying a power to the sense amplifier. The first and second power sources are independent and separate.