A programmable frequency synthesizer (PFS) consists of three serially conted stages: an accumulator, a triangle converter, and a sine shaper. The accumulator is the frequency-generating stage of the synthesizer. It consists of an input latch to store the binary programmed frequency, an adder, an output latch to store the output of the adder, and a clock oscillator. The output frequency of the accumulator can be directly scaled by changing its clocking frequency. The square wave output of the accumulator is divided in frequency by the triangle converter, which produces a triangularly shaped staircase waveform. The sine shaper stage employs diode limiters and filters to produce low-harmonic sinusoids from the triangular staircase.
A direct digital synthesizer capable of generating a desired frequency with small circuitry, low power consumption, and no spurious components. It includes an accumulator for accumulating a frequency control word for each pulse of a clock signal, a D/A converter for converting the accumulation value of the accumulator to an analog voltage, an integrator for smoothing the output of the D/A converter, a comparator for comparing the output of the integrator with a reference voltage, and for producing pulses at timings at which the output of the integrator reaches the reference voltage while the accumulation value of the accumulator is increasing, and a pulse generator for producing pulses in synchronism with the rising edges of the output of the comparator. The output pulses of the pulse generator constitute an output of the direct digital synthesizer.
A direct digital synthesizer that outputs at least a predetermined output frequency related signal from a received digital signal, K, with minimum spurious signal levels. A storage device stores an initial phase value of the digital signal, K, and provides the initial phase value on an output thereof. An adder is provided having a first input for receiving the digital signal, K, having a second input and having an output which provides a summation of signals received on the first and second inputs. A latch has a first input connected to the output of the storage device, has a second input connected to the output of the adder and an output connected to the second input of the adder. The latch also has a third input for receiving a select signal for selecting between receiving on the first and second inputs of the latch. A control circuit provides the select signal in response to one of a plurality of predetermined parameters. The output frequency related signal is provided on the output of the latch. One or more detectors identify a power interrupt of the direct digital synthesizer or a change in the digital signal, K, and provides a detect signal to the control circuit. When a power interrupt or change in K is detected, the control circuit causes the latch to first receive the initial phase value on the first input thereof and then switch to the second input thereof for subsequent operations.
An arithmetic frequency synthesizer comprises one or more parallel/pipelined systolic computing arrays for performing parallel, recursive accumulation functions. Existing very large scale integrated circuit technology may be used to fabricate such arrays. Such a frequency synthesizer may be utilized, for example, to provide scan non-linearity correction, motor hunt compensation and/or polygon signature correction for laser scanners.
In order to deliver an angle-modulated output signal as a function of digital information, the frequency synthesizer delivers an output frequency F.sub.S =(N+k)F.sub.R, where N is the integral part of a number N+k and F.sub.R is a reference frequency. Provision is made for a variable oscillator, an oscillator control loop comprising in series a variable divider having a preselected divisor N, a phase comparator for receiving the reference frequency and a summing device. The synthesizer further comprises a phase accumulator for performing, at the frequency F.sub.R, modulo-M summation of a number G=k(M) applied to its input. The sum and carry outputs of the accumulator are coupled respectively to the summing device in order to deliver a signal for compensating the signal delivered by the phase comparator and to the divider for delivering a control signal to select the divisor N+1. An adder having one output coupled to the input of the phase accumulator receives a constant number g on one input and a number dg which is representative of the digital information on another input.
A direct digital synthesizer (DDS) for generating an output periodic waveform from a stored digital waveform has a linear feedback shift register coonfigured as a counter. The linear feedback shift register is clocked by the internal reference clock of the DDS, and a predetermined output of the linear feedback shift register is detected to provide a control signal. The control signal causes the frequency or phase of the output waveform to be changed according to control parameters input to a control logic circuit. The control logic circuit preloads the new parameter vlaues into appropriate frequency/phase registers which are switched to the input of the accumulator in the DDS on the next cycle of the reference clock when the control signal is detected.
