The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in the fetch cycle, a fourth clock period occurs following a memory read pulse. This fourth clock cycle is required for the application of the microprocessor, but does not involve any addressing of the memory. Accordingly, in accordance with the invention, upon the occurrence of a memory read cycle, during which a normal refresh occurs, the refreshing circuitry is reactivated, so that a further refresh cycle will occur during this fourth clock.
A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.
A computer memory including a memory subsystem controller having a circuit for providing a plurality of block select signals and a raw address. A plurality of memory blocks is provided, with one of the memory blocks being provided for each of the block select signals from the memory subsystem controller. Each of the memory blocks includes random access memory (RAM) devices for storing data, and a refresh circuit for refreshing its associated RAM devices independent of the refreshing of the RAM devices of the other blocks. The refreshing of the refresh circuit occurs, if possible, when its associated memory block is not selected by its corresponding block select signal from the memory subsystem controller. A re-establishing circuit is included in each memory block which receives a row address from the memory subsystem controller and re-establishes the received row address in its RAM devices after they have been refreshed.
A random access memory having blocks of memory cells arranged two-dimensionally in groups associated with pairs of data lines. Each pair of data lines transfers write-data to and read-data from respective groups of memory blocks. A column decoder selects, for a plurality of groups, one memory block from among the blocks in a group to be connected to a corresponding data line in accordance with a column address signal. A section decoder connects the coresponding data lines which were connected to selected ones of the memory blocks to a data input/output circuit.
A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.
A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
