A plurality of single transistor memory cells with electrically charged capacitors and two similar dummy memory cells are electrically coupled in symmetric relationship to a sense amplifier for each row of the disclosed memory circuit. An address signal selects a word line connected to the memory cell on one side of the amplifier and a dummy word line connected to the dummy memory cell on its other side and applies a word signal to the selected word lines, in order to read out electric charges on the capacitors, and the amplifier amplifies a potential difference due to the read charges. For each row two dummy word lines are connected to delay means coupled to the amplifier to form an activating signal for the amplifier by delaying a potential rise developed on the selected dummy word line.
A memory device having an on-chip ECC system includes an array of memory cells, some of which have wider transistors than others so that they have faster access speeds. Data bits are written into ordinary memory cells and the check bits are written into the faster cells in order to make up for the delay associated with the calculation of the check bits.
An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line is used to signal the ECC when data from the DRAM arrays is valid during a fetch operation; the same dummy data line also signals the DRAM arrays when the data from the ECC is valid during a write-back operation.
A semiconductor memory device comprises first and second dummy memory cells. The first dummy memory cell is connected between a normal row line and a dummy column line. The second dummy memory cell is connected to a dummy row line and the dummy column line. The dummy row line is applied with an output voltage of a bias circuit which applies a constant voltage. The second dummy memory cell is used as a reference memory cell and generates a reference potential which is kept unchanged.
