The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.

An output circuit for a semiconductor integrated circuit is improved by reverse biasing the gates of non-selected output field effect transistors (MOSTs). A control MOST, when actuated by a chip-select signal, connects the gate of its associated output MOST with a negative voltage so that the non-selected output MOSTs are completely cut off. The invention avoids the problem which arises with the use of very short channel output MOSTs such that the channel cannot be completely cut off if a zero bias is applied to the gate.

An output circuit which can operate at a high-speed and with a small power consumption is disclosed. The output circuit comprises a first series circuit including first and second transistors, an intermediate junction of the first and second transistors being connected to an output terminal, an impedance means, means for connecting one end of the impedance means to a power voltage terminal, and a third transistor connected between the other end of the impedance means to a second voltage terminal, one and the other ends of the impedance means being connected to control electrodes of the second and first transistors, respectively.

Initial spike noise which occurs, when an IC is switched on, is suppressed by an output control circuit provided between the output terminal of an inner logic circuit and an output circuit of the IC. The output control circuit clamps the input terminal of the output control circuit until the supply voltage builds up to a steady state. The output control circuit comprises two stages each connected between the supply voltage and ground. The first stage has a series connection of a first FET and first resistor, the second stage has a series connection of a second FET, third FET and second resistor. The first FET is controlled by a reset signal and turns off the second FET until the reset signal is released. The second FET turns off the third FET which transmits the output signal of the inner circuit to the output circuit of the IC. When the reset signal is released, the third FET and hence the output circuit begins operation.

In a push-pull switching circuit, whose output transistors are controlled by complementary control signals, one of the gate electrodes which carries a "low" signal is kept just at the threshold voltage of the output transistor to be cut off by means of a transistor substantially identical to the output transistors, the gate electrode and the drain electrode of this transistor being interconnected. The junction of this gate and this drain is connected to the common of two cross-coupled transistors, which are connected by their drains to the gate electrodes of the respective output transistors.