A circuit to permit testing the refresh counter in an integrated circuit memory by writing into cells whose row addresses are determined by the refresh counter.
A dynamic random access memory device is equipped with a test circuit for testing an internal refresh circuit. In a test mode, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated. Further, data is written into the designated memory cell from outside of the memory device, and the data stored in the designated memory cell is then read out to check whether the read-out signal is coincident with the written data.
A semiconductor integrated circuit device which constitutes a dynamic RAM has an automatic refresh circuit that contains a refresh timer circuit. The refresh timer circuit has a program element such as a fuse element. The program element is programmed depending upon the data holding characteristics of the dynamic memory cells. Therefore, the refresh period is changed depending upon the characteristics of the dynamic memory cells. According to this construction, the refresh period changes and, as a result, any undesired refresh operation is prevented from being executed, making it possible to reduce the amount of electric power consumed by the circuit device.
In an information memory device of the type wherein informations are sequentially stored in cells of a memory cell array and read out from the cells according to selected addresses, there are provided an internal address generator for generating an internal address, an address information selector for selecting either one of the internal address and an external address supplied from outside to form a selected address, and an information memory circuit for storing a memory information at a position designated by the selected address and for reading out the information stored in the designated position.
According to the present invention, there is provided a circuit structure capable of carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation. The counter generates a refresh row address. The bit line sense amplifier circuit connected to a bit line pair for transmitting data of a memory cell, consists of the N-channel sense amplifier and the P-channel sense amplifier. The sense amplifier driving circuit supplies respective driving signals for the N-channel sense amplifier and the P-channel sense amplifier. The test control circuit is provided for carrying out the function test of the refresh counter and the measurement of the counter cycle at the time of the refresh operation, and controls the driving signals so as to set one of the N-channel sense amplifier and the P-channel sense amplifier in a non-active state at the time of a test mode.
A semiconductor memory device comprises a test mode reset inhibiting circuit (22). The test mode reset inhibiting circuit (22) comprises a trigger signal generating circuit (31). When the semiconductor memory device is set in hidden fresh mode during a test mode period, a trigger signal (REFCT) is generated from the trigger signal generating circuit (31). As long as the trigger signal (REFCT) is generated, test mode reset is inhibited by the test mode reset inhibiting circuit (22).
