A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge level, and a third detector for detecting whether one of outputs from the first and second detectors and the operand input bit are both in an active state.

A priority encoder for encoding input data by scanning the input data in a predetermined direction, includes: a first voltage section for charging a plurality of output lines to a first voltage level; a plurality of switching elements connected to the plurality of the output lines, each of the plurality of switching elements being turned on in accordance with a value of the input data; and a second voltage section for charging a selected one of the plurality of output lines to a second voltage level different from the first voltage level, through the switching elements which are turned on.

When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input data signal D is input to a 1 detecting circuit and a 0 detecting circuit, which are connected in parallel, while the data latch holds the input data signal D; for example, a 1 detection process for detecting that bit data changes from 0 to 1 or a 0 detection process for detecting that bit data changes from 1 to 0 is performed; and either a 1 detection or a 0 detection output operation, which is selected by a selector circuit 27, is performed. As a result, a bit search process is quickly performed.

A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

A register address specifying circuit capable of, besides accessing a register whose address is specified address, accessing also a register whose register address which is one address different from the specified register address, when executing the instruction for transferring a plurality of register contents, and a data processor which is able to access and transfer two register contents at the same time by comprising the same.