This invention relates to a timing control, for example, a control for reserving a waiting time when a data processor sends or receives data to or from an external device. Dummy cycles for a number of cycles having a processing time equal to the desired waiting time are generated by a dummy instruction. A timing control system is disclosed which is especially suitable for a micro-program system of a pipeline control system.

A data-processing apparatus having a processor, a read-write memory, a data bus, a program counter, a program memory and an instruction register. There is also a feedback finite-state machine possessing a multibit-wide output whose bits are determined in at least two successive machine cycles. This output is connected to a comparator which has its other input connected to the instruction register. A certain equality condition can invalidate the current instruction so that the latter acts as a rapidly performable dummy (NOP) instruction and a program jump can be performed. In a further expansion another multibit-wide output of the finite-state machine can be coupled to the data bus via a decoding circuit.

A microprogram control circuit interrupts high speed clock signals inputted to a processor when a HALT instruction issues from the processor in order to end operation at completion of a program. The clock signal is provided only when a program is in process. Should a program continue beyond a preselected time period without a HALT instruction, a control circuit including a timer detects this condition and interrupts the clock signals to the processor. Either an external signal or an automatic internally generated signal allows the clock signal to again enter the processor, reset the registers and address counter, and restart the program. In an alternative embodiment, abnormal operation causes the program to restart without interrupting the clock signals.

A communications interface and system is configured to allow circumvention recovery of control after radiation) of a microprocessor portion thereof. The communications interface portion, including a hard memory interface device serves as a communications link to the microprocessor. The system is configured so that a transient upset from prompt gamma radiation is detected and a circuit freeze of the stored information in the system is carried out until the transient subsides. The system then restores the microprocessor to the preirradiation condition and resumes operation. Accordingly, the hard memory interface device of the communications interface, controls a READ operation and CLEAR and WRITE operations in addition to generating signals to control the "handshaking" between the hard memory of the communications interface and the aforementioned microprocessor.

A combination watchdog timer and input voltage level detector circuit is coupled to a microcomputer (or microprocessor) for insuring proper operation thereof under various conditions. The watchdog timer is coupled to the microcomputer and is responsive to a status signal output by the microcomputer indicating the operating state thereof. Failure of the watchdog circuit to detect the status signal indicates that the microcomputer has become unstable or is in a locked up condition and causes the watchdog circuit to initiate a microcomputer reset by means of a reset trigger circuit. A voltage level detector is coupled to the input voltage source and to the reset trigger circuit for similarly initiating the resetting of the microcomputer in the event the input voltage to the microcomputer drops below a predetermined value. When power is initially applied, a power up detector coupled between the voltage level detector and the watchdog timer ensures that the reset trigger circuit maintains the microcomputer in a reset condition until the input voltage reaches a predetermined level to permit normal microcomputer operation. The present invention thus ensures that the microcomputer is maintained or is placed in a reset condition in the event of input power transients, upon initial application of power to the microcomputer, and upon the occurrence of irregularities in microcomputer program execution.