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Description  |
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BACKGROUND OF THE INVENTION
In recent years, computers particularly microcomputers, have achieved
noticeable and extensive development. At present, various applications are
being devised to utilize the extensive advantages afforded by
microcomputers which are as effective as, and yet more compact than,
minicomputers.
For example, the microcomputer is applied not only to various control
devices such as those for controlling a process and sequence, but also to
instrumentation data-processing systems, minicomputer and business
systems, and more recently to automobiles and general household
appliances.
The fundamental elements of the microcomputer system are the CPU, memories
and peripheral unit such as an input-output (I/O) device. These elements
are connected by a bus and control signal line.
Referring to FIG. 1 showing the arrangement of a prior art microcomputer
system, the CPU 11 is an arithmetic control unit including an arithmetic
logic unit (hereinafter referred to as the "ALU"), control circuit and
registers and acts as the control portion of the microcomputer system. The
CPU 11 is generally formed of only one or two circuit chips fabricated by
the large scale integration (LSI) technique. The CPU 11 controls the steps
of decoding an instruction issued from a memory 12, carrying out an
arithmetic operation on data read out of the address of the memory 12
specified by the instruction, supplying the result of the arithmetic
operation to the memory 12, transferring program information and data from
the I/O device 13 to the memory 12, and also transmitting data from the
memory 12 to the I/O device 13. The CPU 11 further controls the
designation of an address from which a program is to be read out and also
the execution of the program according to the internal condition of the
CPU 11. The memory 12 receives from the CPU 11 data on a given address and
a control signal for specifying whether data is to be read out of said
address or written therein, and causes the contents of the specified
address to be read out to the CPU 11, or causes data supplied from the CPU
11 to be stored at the specified address.
The memory 12 generally includes a sequential memory and/or a random access
memory (hereinafter referred to as a "RAM"). And the random access memory
may further be categorized as a read-write memory normally admitting of
reading and writing and a read only memory (hereinafter referred to as a
"ROM"). Since the read-write memory is normally called a "RAM", a memory
permitting both reading and writing is defined as a "RAM", and a memory
only capable of effective reading is defined as a "ROM" in the
specification.
The ROM is supplied with prescribed programs and data and the CPU executes
prescribed program processes according to the contents of the ROM.
Data is transmitted from the I/O device 13 to a specified address of the
memory 12 or vice versa according to the contents of an instruction issued
from the CPU 11. The peripheral unit includes not only the aforesaid I/O
device 13 but also an auxiliary memory 14. Data may be transmitted between
the main memory 12 and auxiliary memory 14. The CPU 11, main memory 12,
and I/O device 13 are interconnected by a bus 15. This bus 15 may be a
bidirectional transmission line for transmitting words parallel-by-bit
(two uni-directional bus lines may also be used instead of the
bidirectional bus). A control line 16 includes, for example, a
synchronization timing line, interrupt signal line and instruction line.
The control line 16 is used for transmission of instructions issued from
the CPU 11, timing signals, response signals delivered from the memories
12, 14 and peripheral unit, and interrupt signals.
There will now be described by reference to FIG. 2 the construction of the
prior art CPU 11. The fundamental arrangement of the CPU 11 is broadly
divided into the arithmetic logic system, control system and interface
system. The arithmetic logic system comprises registers and the arithmetic
logic unit (ALU). The register used for arithmetic operation mainly
include an accumulator 21 and the general registers 22. The accumulator 21
is directly used in arithmetic operations and its function is well
understood.
The general registers 22 can be applied to various different purposes such
as arithmetic register, a data register and an index register, etc. In the
present specification, the general registers 22 may be defined as a
general register set including a program counter register, (hereinafter)
referred to as the "PC") and a program status word register, (hereinafter
referred to as the "PSW"), but the PC and PSW may not always be included
in the general register set 22.
The customary practice is to provide 4 to 16 individually addressable
registers in the general register 22 (which are marked by address) may be
specified by the program.
In addition to the above-mentioned accumulator 21 and general registers 22,
there is further provided another type of register referred to as "a
working register 23" which is temporarily used to enhance the efficiency
of arithmetic and control operations. The ALU 24 carries out the addition
and subtraction of numerals expressed by binary codes and logic operations
(AND, OR exclusive OR, etc.) in the form of parallel arranged bits.
Multiplication and division are effected by a combination of addition,
subtraction and shifting functions. A simple form of this shifting
function is carried out by shifting one digit after another in the
accumulator with the number of shifted digits counted by a counter.
Another method of shifting is to provide an exclusive arithmetic logic
unit referred to as "a shifter", thereby shifting a plurality of bits at
once. A counter 25 is provided to count the number of shifted digits and
the number of repeated cycles of multiplication and division.
A principal function of the central processing system is to control the
designation of memory addresses, the decoding and execution of
instructions and the status of, for example, the I/O device. The
designating numerals of the addresses of the memories, 12, 14 are stored
in address registers. Particularly the address from which an instruction
included in a program is to be read out is stored in the PC register 26.
The PC, well known generally, is incrementally advanced by a count of +1 to
specify the succeeding instruction address and holds the executing address
of the current program instruction. The CPU may be further provided with a
stack memory 27 for storing the contents of a return address where
interruption or subroutine functions arise.
In the case of the CPU provided with the stack memory mentioned above, the
stack 27 has push-down and pop-up functions and is such a type of memory
as causes later stored data to be read out earlier (Last-In, First-Out,
LIFO), and is formed of 4 to 16 layers. The function of the stack 27 is
carried out by means of an address register or a stack-control memory
referred to as "a stack pointer 28". Though possessed of the stack
function, some processors are not actually provided with a stack memory,
but utilize the main memory for said stack function with the
above-mentioned type of processor, the stack pointer specifies an address
only in the case of the stack function, causing data to be transmitted
between the main memory and PC.
An instruction read out of the address specified by the program counter 26
is entered into an instruction register 29. The contents of the
instruction register 29 are decoded by an instruction decoder 30 enabling
initiation of various operations.
An output signal from the decoder 30 is delivered to a control circuit 31,
an output from which is applied to the various sections of the
data-processing apparatus in synchronization with a timing signal. The
control method includes a wired-logic method and microprogram method.
According to the wired-logic method, signals representing all the
processing operations are formed through the control gates in the control
circuit. Where an instruction is decoded, then the said control gates
issue control signals to control the various sections of the
data-processing apparatus.
According to a microgram control method typically employed, a set of
instructions are used which are designed to execute the fundamental
operations of the hardware. One instruction (user instruction or macro
instruction) is converted into a combination of micro instructions, which
are executed in succession with this microprogram control method. The
control circuit has a simple arrangement and can be easily expanded or
altered, but tends to be operated at a low speed. This drawback is for the
reason that the complicated logic circuit has been converted into the form
of a program represented by micro instructions. With the microprogram
control method, the program is generally stored in the ROM. The program is
executed through the same sequence of steps as in the aforesaid
wired-logic method, that is, by designating an address of the ROM,
retrieving a microinstruction and entering it into a micro instruction
register, decoding the micro instruction read out of said register and
thereafter issuing control signals. Status control involves the operation
of supplying a specified element with information on the interior
condition of a microcomputer or the status thereof specified by a
microprogram, reading out the information, where necessary, and
determining a control mode by reference to this information. With a
microcomputer provided with a simple form of CPU, a status flip-flop
circuit may be set or reset to preserve status information.
In a microcomputer equipped with a higher grade CPU, an exclusive status
register 32 (FIG. 2) may be provided to store status information. The
respective bits constituting the status register 32 are made to have
previously defined functions, when status information is stored in the
status register 32. The status register 32 is designed to cause the
respective bits to be written therein or read out therefrom. The typical
forms of status include the overflow of the arithmetic logic unit, the all
zeros-all ones status of an accumulator (to prevent division by zero),
mode designation, interrupt mask, fault indication and so forth.
The interface system of the CPU carries the buffing function, processing of
an interruption instruction and synchronous control. The interface system
acts as a sort of window through which data is transmitted between the
processor and the external device. Data is transmitted through an
input-output buffer register 33. Where there is a difference between the
speed at which data is supplied from an external source and the speed at
which the CPU receives the data, then the buffer register 33 acts to
compensate for such difference.
An interrupt signal is a control signal applied from an I/O device to the
processor independently of the operations occurring in the processor.
Where the interrupt instruction-processing circuit 34 of the processor
receives an interrupt instruction, then the internal operations of the
processor are temporarily stopped to carry out the operation demanded by
the interrupt instruction. Interruption has two forms, that is, an
internal interruption resulting from a cause arising within the CPU and an
external interruption arising from a cause mainly related to the I/O
devices external to the processor. The causes of the internal interruption
include, for example the overflow of digits resulting from calculation,
errors in arithmetic operation such as a request for division by zero,
memory errors (parity errors) and abnormal power supply conditions. The
causes of external interruptions mainly include a request for termination
of the operation of an I/O device and a service request made by a terminal
unit. Namely, an external interruption takes place where a unit working
independently of the control of the CPU desires to inform the CPU of the
status of said unit or to be controlled by the CPU. The urgency of the
interruption is classified according to the cause. Where interruption
requests are generated, the CPU accepts those having higher degrees of
urgency or higher priority levels. This is to prevent confusion where two
or more interruption requests arise at the same time. In this case, an
interruption request having a lower degree of urgency is made to wait or
is disregarded. Where an interruption request is accepted, then the
contents of not only the program counter but also various registers (for
example, the status register and general registers) all included in the
processor are temporarily stored in the memory (normally in the main
memory). Thereafter, an interrupt program is executed in response to the
interrupt request. In this case, the contents of the PC are replaced by
the address which indicates the entry of the interrupt program.
Upon completion of the processing of the interrupt program, various data
previously stored in the main memory are read out to the corresponding
registers, and execution of the original program is resumed. This
operation is generally carried out by a separately provided system
program. Transmission of data between the memory and various registers is
effected by more than ten steps. The total length of time required to
execute all the program steps (including the "save" and "unsave"
operations) amounts to several hundreds of milliseconds, thus decreasing
the efficiency of the CPU.
Particularly where a plurality of interrupt requests arise in an extremely
short time interval, for example, several microseconds, it is not too much
to say that the quality of a processor can be determined from the speed at
which an interruption request is executed.
A prior art program status word (hereinafter abbreviated as "PSW") used to
control the execution of an interruption request has a bit arrangement as
shown in FIG. 3. Individual mask bits are assigned to bit positions "0" to
"7".
An interrupt program allotted to bit position "0" is taken to have the
highest degree of urgency or the highest priority level. A bit occupying
the bit position 8 is used as a master mask bit. Where this bit has a
logic level of "1", then the execution of an interrupt program is entirely
inhibited, namely, the CPU will not accept an interruption request.
Various condition or flags are assigned to bits occupying bit positions 9
to 11. The bits 9 to 11 denote the "Carry" flag, "Negative" flag and
"Zero" flag respectively and are used as condition codes.
The PSW having the above-mentioned bit arrangement is allocated to address
1 of the memory, as shown in the FIG. 4. The PC is assigned to address 0,
and data registers and index registers are allocated to addresses 2
through 7. The addresses 8 to 15 receive data on the corresponding restart
addresses of the interrupt programs, namely, linkage information. The
address 4095 is used to store the designating numeral of the starting
address of the main program.
When the CPU accepts a given interrupt request, then all the other
interrupt requests are forced into a wait state. The contents of the PC
are swapped for the contents of that of the addresses 8 to 15 which
corresponds to the accepted interrupt program. The designating numeral of
the restart address of the interruption service routine is stored in the
PC.
With the above-mentioned prior art system, an interrupt program is
processed in accordance with a flow chart shown, for example, in FIG. 8.
First, examination is made of whether the master mask bit has a logic
level of "0" or "1". Under the condition where interrupts are enabled,
namely, when the master mask bit 8 is "0", the interrupt which is accepted
is the one having the highest priority among those interrupts which have
corresponding mask bits which are "1" (enabled). Suppose that the level N
interrupt is accepted, the address (N+8), in which the linkage information
for the level N interrupt is stored, is generated automatically by the
hardware of the CPU. Then the linkage information and the contents of the
PC are swapped. The linkage information itself is the entry address of the
level N interrupt program. After the swap operation, a jump to the
interrupt program takes place and at the same time the return address is
saved in the address (N+8). At this time, the master mask bit 8 is made to
have a logic level of "1", thereby inhibiting any other interrupt program
from being accepted. Thereafter, the contents of the general registers are
saved in the work area of the main memory. This operation is necessary to
resume the execution of the original program after the interrupt program
has been fully processed. However, the aforesaid operations, when
performed by software, consume a great deal of time. Upon completion of
the execution of the interrupt program routine, the contents of the
general registers saved in the work area of the main memory are restored
back to the original general registers by software. The operation of this
software is also time-consuming.
As mentioned above, with the execution of an interrupt program by the prior
art data-processing apparatus, it is necessary temporarily to save in
another area the contents of the general registers, which are later
required after the execution of the interrupt program has been completed,
and to return said contents to the original area after said execution.
Therefore, the above-described prior art data-processing apparatus is
subject to certain limitations in processing data due to the relatively
long time consumed in interrupt control and has a low responsiveness to
interrupts.
When process control tasks are undertaken, it is necessary to handle
interrupt requests issued by various sections of a microcomputer system
and generate required outputs within a prescribed limited length of time.
The above mentioned requests arise at random or at the same time. Requests
occurring at random are supplied to the microcomputer as interrupt
signals. Therefore, the microcomputer should have a quick responsiveness
to these requests and execute them at high speed. To meet the
above-mentioned requirements, a method has already been proposed which is
designed to decrease a number of parts of a microcomputer requiring
process control by applying software. For example, a device has been
developed wherein a flip-flop circuit is provided in the CPU, and the
operation of the flip-flop circuit is changed over according to the
contents of an instruction received. A specific microprocessor proposed to
date includes, for example, the "8080A MICROPROCESSOR" of Intel
Corporation of the United States of America. This "8080A MICROPROCESSOR"
issues an XCHG (exchange registers) instruction for the contents of an H
register to be swapped for those of a D register and also for the contents
of an L register to be swapped for those of an E register and an XTHL
(exchange stack) instruction for the contents of an address of a memory
specified by a stack pointer to be exchanged for those of said H and L
registers. These instructions can indeed decrease the number of steps
required in executing a program, but can not be expected appreciably to
reduce the processing time, because the contents of the registers are
saved in the memory or retrieved therefrom fundamentally by means of
software. In view of the above-mentioned circumstances, another type of
microprocessor has been proposed further to decrease the processing time.
With this proposed microprocessor, a particular register is provided in
the CPU. The work area of the memory disposed outside of the CPU is varied
by changing the contents of the particular register. Such a microprocessor
is described at pages 3 to 7 of "TMS 9900 MICROPROCESSOR DATA MANUAL"
published by Texas Instrument Incorporated of the United States of
America. With this microprocessor, a work space allocated to the external
memory is varied by changing the contents of a work space register
provided in the CPU. Even in this case, a memory unit acting as a work
space register lies outside of the CPU. Therefore, this microprocessor
only necessitates that a larger number of registers be provided. This
microprocessor fails to decrease the processing time, because transmission
of data between the CPU and the external memory consumes a great deal of
time.
SUMMARY OF THE INVENTION
It is accordingly the object of this invention to provide a data processing
apparatus and method for controlling a central processing unit in a manner
to achieve extremely high speed processing.
Another object is to provide a data processing unit and method enabling
utilization of simple software control.
A further object is to provide a data processing apparatus and method
ensuring quick responsiveness to interrupt requests.
To attain the above-mentioned objects, this invention provides a
data-processing apparatus and method wherein a central processing unit
includes at least two groups of memory units, each said group being
capable of acting as a general register set having a plurality of general
registers.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block circuit diagram of a prior art general
data-processing apparatus;
FIG. 2 is a block circuit diagram of the prior art control processing unit
shown in FIG. 1;
FIG. 3 is a diagram illustrating the function to which the respective bits
of the prior art program status word are assigned;
FIG. 4 is a memory map for the prior art data processing apparatus;
FIG. 5 is a flow chart showing the manner in which the contents of the
respective general registers collectively constituting a set are saved and
retrieved when an interrupt program is processed in the prior art
data-processing apparatus;
FIG. 6 is a schematic block circuit diagram of a central processing unit
according to one embodiment of the present invention;
FIG. 7 is a block diagram illustrating the means for specifying the
particular memory unit group which is to be used as a general register set
in the system of FIG. 6;
FIG. 8 is a memory map for the FIG. 6 embodiment of the data-processing
apparatus of the invention;
FIG. 9 is a diagram depicting the function of the respective bits of the
program status word used with the data-processing apparatus of the
invention;
FIG. 10 is a memory map for another embodiment of the data-processing
apparatus of the invention;
FIG. 11 is a memory map showing a common register provided between the
respective sets of general registers; and
FIG. 12 is a block diagram showing the means for specifying a particular
common register for use in the system of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 6 is a schematic block circuit diagram of a central processing unit
(hereinafter referred to as a "CPU") according to one embodiment of the
present invention. The CPU 61 comprises a single circuit chip having a
function register (F register) 62 for decoding an execution instruction;
temporary registers (A, T, B, M) 63 for temporarily storing data supplied
from the function register 62; an arithmetic logic unit 64 for carrying
out arithmetic logic operations such as addition, subtraction, AND, OR and
shift with respect to data received from temporary registers 63; a
microprogram ROM 65 for storing information on the sequence in which data
is processed in the CPU 61; a microbranch control unit 66 for controlling
the branching of a microprogram; memory means 67 provided with a plurality
of (for example, eight) sets of memory units, each said set being capable
of acting as a general register set including a program counter (not
shown) for storing instruction status data; a memory control circuit 68
including, for example, a general register set pointer for specifying that
memory unit group of the memory means 67 which is to be used as a general
register set; a status control unit 69 including flip-flop registers for
storing the current status of the CPU 61 and a circuit for controlling the
status of said flip-flop registers; an interrupt control unit 70 including
mask elements for interrupt requests and a circuit for selecting one of a
plurality of simultaneously submitted interrupt requests which has the
highest degree of urgency or priority; a common bus control unit 71 for
controlling transmission of data between the CPU and the memory means or
an input-outut device; a timing pulse generator 72 for producing clock
pulses for defining the timing in which data is stored in the function
register 62, temporary register 63 and general registers; and a special
function unit 73 used, for example, to expand a bit arrangement.
With the CPU of the data-processing apparatus of this invention, data is
transmitted between the respective block sections of said CPU in almost
the same manner as in the prior art CPU, and the same types of control
signals are used, description of said data transmission and control
signals being omitted.
There will now be described by reference to FIG. 7 the improvement in the
operation of the memory means and memory control circuit, which are
achieved by the present invention.
The memory means 67 comprises a plurality of (for example, eight) memory
unit groups M.sub.0 to M.sub.7 which are collectively formed of a large
number of absolute addresses 0 to 63. These memory unit groups M.sub.0 to
M.sub.7 are each capable of acting as a general register set, having a
plurality of (for example, eight) general registers R.sub.0 to R.sub.7.
The memory unit groups (M.sub.0 to M.sub.7) are divided from the memory
means 67 and each group corresponds to the divided block of the memory
means 63.
The memory control circuit 68 comprises a general register set pointer
register 710 including, for example, three bits, as means for specifying a
particular general register set. This general register set pointer
register specifies that of the plural memory unit groups which is to be
used as a general register set. Where the 3-bit pointer of a general
register set is represented by a binary code of "000", then the memory
unit group M.sub.0 is selected as a general register set. Where said 3-bit
pointer is expressed by the binary code "111", then the memory unit group
M.sub.7 is designated as a general register set.
The memory control circuit 68 also include | | |
