An image pattern control system of the type having a dynamic memory which operates during a first period to read and rewrite the contents of memory according to address data sent from an address register and to refresh stored data according to the output of a refresh counter during a subsequent second period. The first and second periods are switched according to the output of a zoom ratio hold register.
A memory address signal for a display memory is generated from a memory address generating circuit. The memory address generating circuit has an offset register and a memory address counter in addition to a memory address register. The offset register stores an offset value corresponding to a difference between a width of the display memory and a width of a display picture in a scanning direction. The memory address counter counts up a character clock in order to deliver the memory address signal after loading a start address of each horizontal scanning line of the display picture. At the end of each horizontal scanning line, an adder adds the offset value to the memory address signal. The addition thereof is loaded into the address register as the start address of the next horizontal scanning line.
In an image display apparatus, a frame memory for storing original data and a plurality of display memories for storing data to be displayed are used as memories for storing image data. Data transfer from the frame memory to the display memories is performed in accordance with a DMA scheme. The display memories as destinations of the data transfer are selectively switched. Since the image data transfer from the display memories is performed through a programmable data conversion memory, data conversion as image processing can be performed. The image data is read out from each of the display memories and is displayed on each of a plurality of display systems. An address signal for reading out at least a desired part of the image data from the frame memory is generated in synchronism with a common sync signal used when the image data is read out from the display memories.
A high definition bit mapped page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Eah beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). The invention utilizes CRTs with shaped electron beams, a bit map for storing bits utilized for generating bit patterns which are used to control the shaped electron beams.
The present invention relates to a capability present within a graphics display terminal wherein a zoom operation may be accomplished, the width of each of the lines of the zoomed image being maintained at a one pixel width regardless of the degree or amount of magnification of the zoomed image. This is accomplished by utilizing the firmware stored in the processor to perform the magnification of the image therein, prior to the storage of the appropriate binary data in the video display memory, the binary data being the pixel representation of the displayed image. Since the magnification of the image takes place prior to storage of the binary data in the video display memory, the graphics display terminal of the present invention can use this binary data to display an image, a zoomed image, the width of each line being equal to, approximately, a one pixel width. Therefore, despite the degree of magnification of the zoomed image, a very discernable, clear image will be displayed on the CRT.
A display control circuit comprises dynamic memory chips as a video RAM for storing pattern data or character codes to be displayed on a screen, and a read controller for generating a reading address (including a raster address and a memory address). For refreshing all memory cells for the dynamic memory chips within a predetermined refresh period, the circuit further comprises an address converter for supplying a part of the raster address and a part of the memory address to a row address of the memory chips and for supplying all or a part of the remaining reading address to a column address thereof so that a part of the raster address is assigned to the lower bit location of the row address.
