A multiprocessor system, the kind in which two or more separate processor modules are interconnected for two power supplies, provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user program. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.
This application is a division of parent Application Ser. No. 721,043 filed Sept. 7, 1976, now U.S. Pat. No. 4,228,496, and entitled "Multiprocessor System" and claims the benefit of the filing date of the parent Application.
An auxiliary connector circuit is used within an electronic system (10) which comprises a plurality of removable circuit cards (14, 16, 18, 20, 22, 24, 26) which are mounted within a cabinet (12). Before the circuit card (16) is removed from the cabinet (12), a power cable (44) is connected by means of engaging a plug (46) to a socket (34). When this occurs a DATA OUT ENABLE signal at a line (65) drives three-state devices (86, 88, 90, 92, 94, 96, 98 and 100) to a high impedance state to isolate a memory array (78) from a data bus (102). This high impedance prevents any transients from being transmitted through the data bus (102) when the card (16) is removed from the cabinet (12). After the card (16) is removed from the cabinet (12), the power cable (44) can be disconnected from the card (16) or the card (16) can be tested to evaluate the components mounted on the card (16).
An entry level data processing system is expandable, with low overhead, by a factor of two to a partitionable upgraded data processing system. This entry level system includes: 1) one system bus, 2) a central processing module (CPM), an input/output module (IOM), and a system control module (SCM)--all of which have one system bus port coupled to the system bus, 3) a memory module coupled via a memory bus to the system control module, and 4) a system expansion interface through which the entry level system is expanded to the upgraded system. In one particular preferred embodiment, the system expansion interface consists of a) a first connector on the SCM for externally connecting to and communicating with the memory bus, b) a second connector on the SCM for externally connecting to and communicating with the system bus, and c) an extension of the system bus through a switch in the SCM and a third connector on the SCM for externally connecting to and communicating with the extended system bus. To expand the entry level system to the upgraded system, a duplicate copy of the entry level data processing system as recited in 1-4 above is added along with a respective three port bus expansion module (BEM) in each copy of the entry level data processing system. This BEM, in each particular entry level system, intercouples the first and second connectors on the SCM of that same system to the third connector on the SCM of the other entry level system.
A data processing system having hierarchical memories comprised of buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by part of the set-selection address bits.
Method and apparatus for allowing multiple enclosures (10) to be connected so that their respective motherboards (15) together define a single bus. System-wide arbitration is carried out asynchronously on an enclosure basis while arbitration within each enclosure occurs synchronously. A bus repeater (20, 25, 25') is provided at each of the upstream and downstream ends of each enclosure's motherboard. The upstream bus repeater (20) in a given enclosure is coupled by a flexible connector cable (30) to the downstream bus repeater (25, 25') in the enclosure immediately upstream. One of the bus repeaters (say the upstream one) has the status as master or arbiter while the other has the status of a slave. The connector cables have two sets of lines (32, 35), thereby allowing the bus repeaters to pass two basic types of signals: (a) bused signals (address, data) which are made available to the relevant unit boards; and (b) private signals which are passed only to the bus repeaters. The set of private signals comprises two subsets (i) downstream bound, and (ii) upstream bound, each subset of which includes request, busy, grant, and arbitrate signals. Within each enclosure, the bus repeaters monitor the local bus request and bus busy lines, and logically combine them with the upstream bound and downstream bound private request and busy signals.
Modularly Structured Digital Communications System having Operations-Oriented Communication Means. The operations-oriented communication means are distributed in three structure levels such that operating technology apparatus program modules that are associated with types of terminal equipment are provided in a line technology task structure for generating logical operating technology status messages or for setting data for operating technology terminal equipment. A coordination program module for controlling the operations-oriented information and data flow is provided in a coordination task structure and at least one application program module for sequencing application-oriented functions is provided in an application task structure.
