An arbitration system having a common resource and a first arbitration logic. The first arbitration logic includes a plurality of logic sections. Each one of the logic sections is fed a corresponding one of a plurality of request signals for the common resource. The logic sections produce, in response to request signals, a corresponding one of a plurality of grant signals. Each one of such sections has: a corresponding one of a plurality of first data storage elements, each one of such storage elements storing a corresponding one of the grant signals in response to first clock pulses, such stored grant signals being provided at outputs of the storage elements. The arbitration system includes a plurality of transmission channels, each one having an input coupled to a corresponding one of the outputs of the plurality of first data storage elements. The plurality of transmission channels pass the grant signals stored in the first data storage elements to outputs of the transmission channels. Also provided is a second arbitration logic. The second arbitration logic includes a second plurality of data storage elements, each one thereof having an input coupled to an output of a corresponding one of the transmission channels. The grant signals at the outputs of the channels are stored in the second plurality of storage elements in response to clock pulses from a second source of clock pulse. The clock pulses produced by the first source of clock pulses are independent of the clock pulses produced by the second source of clock pulses. The second arbitration logic also includes a plurality of majority gates. Each one of the gates has a plurality of inputs. Each one of such plurality of inputs is coupled to an output of each of the second plurality of data storage elements. Each one of the majority gates produces an output in accordance with a majority of the data fed thereto.

An arbiter cooperating with p.n processing units grouped into p levels each comprising n processing units. An elementary arbiter is assigned to each level, and a central arbiter attributes cyclically the priority to each level. The central arbiter comprises essentially a memory programmed for attributing a single priority to each level.

A cross-connect circuit for coupling each of a plurality of processors to a memory module selected from a plurality of such modules, provided the module in question has not been identified for connection to another of the processors is disclosed. The circuit is preferably organized as a bit-sliced chip. The connections made by the cross-connect circuit can be changed after each memory cycle.

A triple modular redundancy computing system including three asynchronously connected processing elements, each having its own memory, a plurality of arbiters cross connecting processor elements for enforcing synchronization for tasks and for voting arbitration on output and without voting for inputs.

Interrupt requests of different priorities, presented by various interrupt sources (0 to 3), are transferred through control ST, in an associative storage and selection process, into preprocessing elements PE0 and PE1. These elements are variably assigned by controls ST to receive and preprocess requests of associated priority. The preprocessing generates a starting address of a program routine for servicing the respective request. This address is transferred to a common processor which executes the routine. The preprocessing elements can be structured to rapidly generate a succession of different starting addresses relative to several interrupt requests having the priority assigned to that element.