A display refresh system wherein a RAM refresh buffer is tightly packed. Line start addresses in the buffer are determined by the line length such as eighty characters. With each of the lines in the refresh buffer being normally a binary number such as 128 characters in length the line start addresses are such that they do not coincide with the beginning of each line in the buffer. To assure packing they are interspersed each 80 positions sequentially within the buffer. A processor loads the address of each line start character into the pointer area of the refresh buffer. A line counter is used which counts the lines being displayed on the display. The RAM refresh buffer which contains the line start addresses and character data is first addressed by the line counter output to provide the line address. Since the refresh buffer is used as the line pointer register the output bus for pointer data and character data is common. Once the address of the first character in a line is read from the pointer area in the refresh buffer it is loaded into the refresh buffer address counter which then controls the sequential reading of characters in that line from the refresh buffer onto the data bus. Following the reading of each line the sequence is repeated, e.g., the line counter is incremented, its' count used to address the pointer register and the address contained in the pointer register loaded into the refresh buffer address counter.
In providing overlapped displays of characters and graphics on a display unit, character data are arranged in the order of rows, while graphic data are divided into blocks corresponding to the rows of the character data and the data, which are extracted from the respective blocks in the order of lines, are arranged for each line in the order of the blocks. This eliminates the necessity of providing a remainder of address for each row which is instead provided at the end of each line of the graphic data so as to permit the transition to the next line by shifting the high-order digit of the address, and accordingly the utilization efficiency of a RAM is increased.
A method and apparatus in which data defining a high definition video frame are written into a memory in a manner so that the data can be linearly accessed from the memory in a selected (interlaced or progressive) format. In a preferred embodiment in which the data are written into a two megabyte memory in blocks of 128 pixels, with a 14-bit address for each block, the invention enables SMPTE-240M format high definition video data to be written into memory in a manner so that the data can be linearly accessed from memory in either an interlaced format or a progressive format. In an embodiment for storing (1920.times.1080)=2,073,600 pixels defining a high definition video frame, the apparatus of the invention includes a two megabyte memory and a thirty-two kilobyte PROM (or PAL) circuit. The thirty-two kilobyte circuit implements two look-up tables, each having a size of 16,384 bytes. In an interlace storage mode, the apparatus employs a first one of the look-up tables to assign interlaced format memory addresses to the pixel blocks being written into memory (so that the data can be linearly accessed from memory in interlaced format). In a progressive storage mode, the apparatus employs the other look-up table to assign "progressive format" memory addresses to the pixel blocks being written into memory (so that the data can be linearly accessed from memory in progressive format).
A memory address signal for a display memory is generated from a memory address generating circuit. The memory address generating circuit has an offset register and a memory address counter in addition to a memory address register. The offset register stores an offset value corresponding to a difference between a width of the display memory and a width of a display picture in a scanning direction. The memory address counter counts up a character clock in order to deliver the memory address signal after loading a start address of each horizontal scanning line of the display picture. At the end of each horizontal scanning line, an adder adds the offset value to the memory address signal. The addition thereof is loaded into the address register as the start address of the next horizontal scanning line.
A storage module which can be inserted into a data processing apparatus, such as a dictating apparatus, includes an at least partly random accessible storage device (5) for the storage of digital data signals and an access device for serially accessing storage locations in the storage device. The storage device requires refreshing and cooperates with a refresh device (6) for refreshing data signals stored in the storage device (5). The refresh device (6) includes additional storage devices (11) which store, upon writing in the storage locations of the storage device (5), start addresses and stop addresses from the access device (9), under the control of a control circuit (12). Only storage locations which are situated between a pair of start and stop addresses are timely refreshed via a refresh control device (20). Such a storage module is preferably used in conjunction with the dictating apparatus for the storage of speech signals.
An apparatus and method for controlling a bit-mapped CRT raster display where a processor stores a bit-map of a CRT display frame in a buffer memory as strings of data words representative of bit-maps for single scan lines of the display. Associated with each string is a pointer which contains the starting address of the string which maps the next scan line. A controller accesses the buffer memory to output the data words of each string to a serializer in synchronism with the raster to generate a CRT video signal. After each string the controller accesses the buffer memory to get the pointer to the next string. In response to a initialization signal from the processor the controller obtains the pointer to the string associated with the first scan line from predetermined locations in memory. Alternatively the processor may directly load the controller with the initial pointer prior to each raster frame. The processor may share the buffer memory with the controller on a cycle-stealing basis to construct new strings. The processor may then easily modify the display by linking and unlinking old and new strings by simple modifications of pointers during the time between raster frames.
