The invention disclosed is a system for receiving, storing and retransmitting voice messages. The system includes a plurality of digital computers operating independently in parallel to supervise the system's operation. The system also includes a conversion subsystem to which a plurality of telephone lines may be connected. The subsystem converts between analog telephone signals and digital data which the system uses for message storage. The conversion subsystem includes a plurality of semi-autonomous sub-subsystems, one per telephone line connected to the system. Each sub-subsystem includes a microprocessor and a random access memory for storing the microprocessor's program and for temporarily storing the digitized voice data. The microprocessor monitors the status of the telephone line and controls the operation of the sub-subsystem's conversion of signals between analog telephone signals and the digital data stored within the system. The system also includes a mass storage subsystem in which digitized voice messages may be stored indefinitely. Multiple, semi-autonomous data transfer paths interconnect the mass storage subsystem and each sub-subsystem to which individual telephone lines are connected. The presence of these multiple, semi-autonomous data transfer paths over which the digitized voice messages are transmitted adapts the system for highly reliable operation. The reliable operation of the system is further enhanced by means of error detection of multiple simultaneous sub-subsystem selection. This selection error detecting means automatically and instantaneously terminates sub-subsystem selection if an error is detected.

This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs require up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Errors occurring during data communications in a data processor communication network are routed by way of an arbitration module to a maintenance and processor. In the event of an error, the module which detects the error immediately terminates its present operation and, after gaining access to the communication bus, reports the error to the arbiter. In so doing, the error reporting module sets an error bit on an error signal line that forms part of the command bus. When the arbiter sees the error bit line set, it ignores the destination address produced by the logical-physical address table which identifies the other participant (destination module) in the transfer in which the error arose, and, instead, substitutes the physical address of the maintenance processor as the intended recipient of the transfer. When the maintenance processor sees it physical address line set, it can proceed to analyze the error report. Since the identities of the source and destination addresses of the participants in the transfer in which the error arose are defined by the contents of the source and destination portions of the address bus, the maintenance processor merely needs to read these buses to learn the location of each module participating in the error transfer.

A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors. Three differing individual requestor bandwidths=data-transfer-bit width/data-transfer-period (144 bits/30 nanosecond, 72 bits/120 nanosecond or 248 bits/240 nanosecond) are intermixedly and simultaneously (to the limit of addressing possibility) supported on 8 memory banks each of which does output 144 bits per 90 nanoseconds.

A cross-connect circuit for coupling each of a plurality of processors to a memory module selected from a plurality of such modules, provided the module in question has not been identified for connection to another of the processors is disclosed. The circuit is preferably organized as a bit-sliced chip. The connections made by the cross-connect circuit can be changed after each memory cycle.